XC3S5000-5FGG676C Datasheet, PDF (4/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Introduction and Ordering Information
power, the configuration data is written to the FPGA using any of five different modes: Master Parallel, Slave Parallel, Master
Serial, Slave Serial, and Boundary Scan (JTAG). The Master and Slave Parallel modes use an 8-bit-wide SelectMAP port.
The recommended memory for storing the configuration data is the low-cost Xilinx Platform Flash PROM family, which
includes the XCF00S PROMs for serial configuration and the higher density XCF00P PROMs for parallel or serial
configuration.
I/O Capabilities
The SelectIO feature of Spartan-3 devices supports eighteen single-ended standards and eight differential standards as
listed in Table 2. Many standards support the DCI feature, which uses integrated terminations to eliminate unwanted signal
reflections.
Table 2: Signal Standards Supported by the Spartan-3 Family
Standard
Category
Description
V_CCO (V)
Single-Ended
GTL
Gunning Transceiver Logic
N/A
HSTL
High-Speed Transceiver Logic
1.5
1.8
LVCMOS
Low-Voltage CMOS
1.2
1.5
1.8
2.5
3.3
LVTTL
Low-Voltage Transistor-Transistor Logic
3.3
PCI
Peripheral Component Interconnect
3.0
SSTL
Stub Series Terminated Logic
1.8
2.5
Differential
LDT
(ULVDS)
Lightning Data Transport (HyperTransport™)
2.5
Logic
LVDS
Low-Voltage Differential Signaling
LVPECL
Low-Voltage Positive Emitter-Coupled Logic
2.5
RSDS
Reduced-Swing Differential Signaling
2.5
HSTL
Differential High-Speed Transceiver Logic
1.8
SSTL
Differential Stub Series Terminated Logic
2.5
Class
Terminated
Plus
I
III
I
II
III
N/A
N/A
N/A
N/A
N/A
N/A
33 MHz⁽¹⁾
N/A (±6.7 mA)
N/A (±13.4 mA)
I
II
N/A
Standard
Bus
Extended Mode
N/A
N/A
II
II
Symbol
(IOSTANDARD)
GTL
GTLP
HSTL_I
HSTL_III
HSTL_I_18
HSTL_II_18
HSTL_III_18
LVCMOS12
LVCMOS15
LVCMOS18
LVCMOS25
LVCMOS33
LVTTL
PCI33_3
SSTL18_I
SSTL18_II
SSTL2_I
SSTL2_II
LDT_25
LVDS_25
BLVDS_25
LVDSEXT_25
LVPECL_25
RSDS_25
DIFF_HSTL_II_18
DIFF_SSTL2_II
DCI
Option
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
No
No
Yes
No
Yes
Yes
No
Yes
No
Yes
No
No
Yes
Yes
Notes:
1. 66 MHz PCI is not supported by the Xilinx IP core although PCI66_3 is an available I/O standard.
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
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