XC3S5000-5FGG676C Datasheet, PDF (122/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Pinout Descriptions
All VCCAUX inputs must be connected together and to the +2.5V voltage supply. Furthermore, there must be sufficient
supply decoupling to guarantee problem-free operation, as described in XAPP623.
Because VCCAUX connects to the DCMs and the DCMs are sensitive to voltage changes, be sure that the VCCAUX supply
and the ground return paths are designed for low noise and low voltage drop, especially that caused by a large number of
simultaneous switching I/Os.
GND Type: Ground
All GND pins must be connected and have a low resistance path back to the various VCCO, VCCINT, and VCCAUX
supplies.
Pin Behavior During Configuration
Table 79 shows how various pins behave during the FPGA configuration process. The actual behavior depends on the
values applied to the M2, M1, and M0 mode select pins and the HSWAP_EN pin. The mode select pins determine which of
the DUAL type pins are active during configuration. In JTAG configuration mode, none of the DUAL-type pins are used for
configuration and all behave as user-I/O pins.
All DUAL-type pins not actively used during configuration and all I/O-type, DCI-type, VREF-type, GCLK-type pins are high
impedance (floating, three-stated, Hi-Z) during the configuration process. These pins are indicated in Table 79 as shaded
table entries or cells. These pins have a pull-up resistor to their associated VCCO if the HSWAP_EN pin is Low. When
HSWAP_EN is High, these pull-up resistors are disabled during configuration.
Some pins always have an active pull-up resistor during configuration, regardless of the value applied to the HSWAP_EN
pin. After configuration, these pull-up resistors are controlled by Bitstream Options.
• All the dedicated CONFIG-type configuration pins (CCLK, PROG_B, DONE, M2, M1, M0, and HSWAP_EN) have a
pull-up resistor to VCCAUX.
• All JTAG-type pins (TCK, TDI, TMS, TDO) have a pull-up resistor to VCCAUX.
• The INIT_B DUAL-purpose pin has a pull-up resistor to VCCO_4 or VCCO_BOTTOM, depending on package style.
After configuration completes, some pins have optional behavior controlled by the configuration bitstream loaded into the
part. For example, via the bitstream, all unused I/O pins can be collectively configured as input pins with either a pull-up
resistor, a pull-down resistor, or be left in a high-impedance state.
Table 79: Pin Behavior After Power-Up, During Configuration
Configuration Mode Settings <M2:M1:M0>
Pin Name
Serial Modes
SelectMap Parallel Modes
Master <0:0:0> Slave <1:1:1> Master <0:1:1> Slave <1:1:0>
I/O: General-purpose I/O pins
IO
IO_Lxxy_#
DUAL: Dual-purpose configuration pins
IO_Lxxy_#/
DIN/D0
DIN (I)
DIN (I)
D0 (I/O)
D0 (I/O)
IO_Lxxy_#/
D1
D1 (I/O)
D1 (I/O)
IO_Lxxy_#/
D2
D2 (I/O)
D2 (I/O)
IO_Lxxy_#/
D3
D3 (I/O)
D3 (I/O)
IO_Lxxy_#/
D4
D4 (I/O)
D4 (I/O)
JTAG Mode
<1:0:1>
Bitstream
Configuration
Option
UnusedPin
UnusedPin
Persist UnusedPin
Persist UnusedPin
Persist UnusedPin
Persist UnusedPin
Persist UnusedPin
DS099 (v3.1) June 27, 2013
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Product Specification
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