XC3S5000-5FGG676C Datasheet, PDF (72/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: DC and Switching Characteristics
Table 42: Setup and Hold Times for the IOB Input Path (Cont’d)
Symbol
Description
Conditions
Hold Times
T_IOICKP
Time from the active transition at the IFF’s
ICLK input to the point where data must be
held at the Input pin. No Input Delay is
programmed.
LVCMOS25⁽³⁾,
IOBDELAY = NONE
T_IOICKPD
Time from the active transition at the IFF’s
ICLK input to the point where data must be
held at the Input pin. The Input Delay is
programmed.
LVCMOS25⁽³⁾,
IOBDELAY = IFD
Set/Reset Pulse Width
T_{RPW_IOB}
Minimum pulse width to SR control input
on IOB
Device
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
All
Speed Grade
-5
-4
Min
Min
Units
-0.55
-0.55
ns
-0.29
-0.29
ns
-0.29
-0.29
ns
-0.55
-0.55
ns
-0.55
-0.55
ns
-0.55
-0.55
ns
-0.61
-0.61
ns
-0.68
-0.68
ns
-2.74
-2.74
ns
-3.00
-3.00
ns
-2.90
-2.90
ns
-3.24
-3.24
ns
-3.55
-3.55
ns
-4.57
-4.57
ns
-4.96
-4.96
ns
-5.09
-5.09
ns
0.66
0.76
ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 48 and are based on the operating conditions set forth in
Table 32 and Table 35.
2. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, add the
appropriate Input adjustment from Table 44.
3. These hold times require adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, subtract
the appropriate Input adjustment from Table 44. When the hold time is negative, it is possible to change the data before the clock’s active
edge.
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
72