XC3S5000-5FGG676C Datasheet, PDF (102/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: DC and Switching Characteristics
Table 67: Timing for the Master and Slave Parallel Configuration Modes (Cont’d)
Symbol
Description
Slave/
Master
Clock Timing
T_CCH
T_CCL
F_CCPAR
CCLK input pin High pulse width
CCLK input pin Low pulse width
Frequency of the clock
signal at the CCLK input
pin
No bitstream
compression
Not using the BUSY pin⁽⁴⁾
Using the BUSY pin
With bitstream compression
During STARTUP phase
ΔF_CCPAR
Variation from the CCLK output frequency set using the BitGen option
ConfigRate
Slave
Master
All Speed Grades
Units
Min
Max
5
5
0
0
0
0
–50%
∞
∞
50
66
20
50
+50%
ns
ns
MHz
MHz
MHz
MHz
–
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 32.
2. Some Xilinx documents may refer to Parallel modes as "SelectMAP" modes.
3. RDWR_B is synchronized to CCLK for the purpose of performing the Abort operation. The same pin asynchronously controls the driver
impedance of the D0 - D7 pins. To avoid contention when writing configuration data to the D0 - D7 bus, do not bring RDWR_B High when
CS_B is Low.
4. In the Slave Parallel mode, it is necessary to use the BUSY pin when the CCLK frequency exceeds this maximum specification.
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
102