XC3S5000-5FGG676C Datasheet, PDF (70/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: DC and Switching Characteristics
Table 41: System-Synchronous Pin-to-Pin Setup and Hold Times for the IOB Input Path
Speed Grade
Symbol
Description
Conditions
Device
-5
-4
Min
Min
Setup Times
T_PSDCM
When writing to the Input
Flip-Flop (IFF), the time from the
setup of data at the Input pin to
the active transition at a Global
Clock pin. The DCM is in use. No
Input Delay is programmed.
LVCMOS25⁽²⁾,
IOBDELAY = NONE,
with DCM⁽⁴⁾
XC3S50
2.37
2.71
XC3S200
2.13
2.35
XC3S400
2.15
2.36
XC3S1000
2.58
2.95
XC3S1500
2.55
2.91
XC3S2000
2.59
2.96
XC3S4000
2.76
3.15
T_PSFD
When writing to IFF, the time from
the setup of data at the Input pin
to an active transition at the
Global Clock pin. The DCM is not
in use. The Input Delay is
programmed.
LVCMOS25⁽²⁾,
IOBDELAY = IFD,
without DCM
XC3S5000
2.69
3.08
XC3S50
3.00
3.46
XC3S200
2.63
3.02
XC3S400
2.50
2.87
XC3S1000
3.50
4.03
XC3S1500
3.78
4.35
XC3S2000
4.98
5.73
XC3S4000
5.25
6.05
XC3S5000
5.37
6.18
Hold Times
T_PHDCM
When writing to IFF, the time from
the active transition at the Global
Clock pin to the point when data
must be held at the Input pin. The
DCM is in use. No Input Delay is
programmed.
LVCMOS25⁽³⁾,
IOBDELAY = NONE,
with DCM⁽⁴⁾
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
–0.45
–0.12
–0.12
–0.43
–0.45
–0.40
–0.05
–0.05
–0.38
–0.40
XC3S2000
–0.47
–0.42
XC3S4000
–0.61
–0.56
XC3S5000
–0.62
–0.57
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
70