XC3S5000-5FGG676C Datasheet, PDF (83/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: DC and Switching Characteristics
Table 48: Test Methods for Timing Measurement at I/Os (Cont’d)
Signal Standard
(IOSTANDARD)
DIFF_SSTL2_II
DIFF_SSTL2_II_DCI
V_REF (V)
-
Inputs
V_L (V)
V_ICM – 0.75
V_H (V)
V_ICM + 0.75
Outputs
R_T (Ω)
50
V_T (V)
1.25
Notes:
1. Descriptions of the relevant symbols are as follows:
VREF – The reference voltage for setting the input switching threshold
VICM – The common mode input voltage
VM – Voltage of measurement point on signal transition
VL – Low-level test voltage at Input pin
VH – High-level test voltage at Input pin
RT – Effective termination resistance, which takes on a value of 1MW when no parallel termination is required
VT – Termination voltage
2. The load capacitance (CL) at the Output pin is 0 pF for all signal standards.
3. According to the PCI specification.
Inputs and
Outputs
V_M (V)
V_ICM
The capacitive load (C_L) is connected between the output and GND. The Output timing for all standards, as published in the speed files
and the data sheet, is always based on a C_L value of zero. High-impedance probes (less than 1 pF) are used for all measurements.
Any delay that the test fixture might contribute to test measurements is subtracted from those measurements to produce the
final timing numbers as published in the speed files and data sheet.
Using IBIS Models to Simulate Load Conditions in Application
IBIS Models permit the most accurate prediction of timing delays for a given application. The parameters found in the IBIS
model (V_REF, R_REF, and V_MEAS) correspond directly with the parameters used in Table 48, V_T, R_T, and V_M. Do not confuse
V_REF (the termination voltage) from the IBIS model with V_REF (the input-switching threshold) from the table. A fourth
parameter, C_REF, is always zero. The four parameters describe all relevant output test conditions. IBIS models are found in
the Xilinx development software as well as at the following link.
http://www.xilinx.com/support/download/index.htm
Simulate delays for a given application according to its specific load conditions as follows:
1. Simulate the desired signal standard with the output driver connected to the test setup shown in Figure 35. Use
parameter values V_T, R_T, and V_M from Table 48. C_REF is zero.
2. Record the time to V_M.
3. Simulate the same signal standard with the output driver connected to the PCB trace with load. Use the appropriate IBIS
model (including V_REF, R_REF, C_REF, and V_MEAS values) or capacitive value to represent the load.
4. Record the time to V_MEAS.
5. Compare the results of steps 2 and 4. The increase (or decrease) in delay should be added to (or subtracted from) the
appropriate Output standard adjustment (Table 47) to yield the worst-case delay of the PCB trace.
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
83