XC3S5000-5FGG676C Datasheet, PDF (126/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Pinout Descriptions
Table 80: Bitstream Options Affecting Spartan-3 Device Pins (Cont’d)
Affected Pin Name(s)
CCLK
CCLK
PROG_B
DONE
DONE
M2
M1
M0
HSWAP_EN
TDI
TMS
TCK
TDO
Bitstream Generation Function
After configuration, this bitstream option either pulls CCLK to VCCAUX via
a pull-up resistor, or allows CCLK to float.
For Master configuration modes, this option sets the approximate
frequency, in MHz, for the internal silicon oscillator.
A pull-up resistor to VCCAUX exists on PROG_B during configuration.
After configuration, this bitstream option either pulls PROG_B to VCCAUX
via a pull-up resistor, or allows PROG_B to float.
After configuration, this bitstream option either pulls DONE to VCCAUX via
a pull-up resistor, or allows DONE to float. See also DriveDone option.
If set to Yes, this option allows the FPGA’s DONE pin to drive High when
configuration completes. By default, the DONE is an open-drain output
and can only drive Low. Only single FPGAs and the last FPGA in a
multi-FPGA daisy-chain should use this option.
After configuration, this bitstream option either pulls M2 to VCCAUX via a
pull-up resistor, to ground via a pull-down resistor, or allows M2 to float.
After configuration, this bitstream option either pulls M1 to VCCAUX via a
pull-up resistor, to ground via a pull-down resistor, or allows M1 to float.
After configuration, this bitstream option either pulls M0 to VCCAUX via a
pull-up resistor, to ground via a pull-down resistor, or allows M0 to float.
After configuration, this bitstream option either pulls HSWAP_EN to
VCCAUX via a pull-up resistor, to ground via a pull-down resistor, or allows
HSWAP_EN to float.
After configuration, this bitstream option either pulls TDI to VCCAUX via a
pull-up resistor, to ground via a pull-down resistor, or allows TDI to float.
After configuration, this bitstream option either pulls TMS to VCCAUX via
a pull-up resistor, to ground via a pull-down resistor, or allows TMS to float.
After configuration, this bitstream option either pulls TCK to VCCAUX via
a pull-up resistor, to ground via a pull-down resistor, or allows TCK to float.
After configuration, this bitstream option either pulls TDO to VCCAUX via
a pull-up resistor, to ground via a pull-down resistor, or allows TDO to float.
Option
Variable
Name
CclkPin
ConfigRate
ProgPin
DonePin
DriveDone
M2Pin
M1Pin
M0Pin
HswapenPin
TdiPin
TmsPin
TckPin
TdoPin
Values
(Default)
• Pullup
• Pullnone
• 3, 6, 12, 25,
50
• Pullup
• Pullnone
• Pullup
• Pullnone
• No
• Yes
• Pullup
• Pulldown
• Pullnone
• Pullup
• Pulldown
• Pullnone
• Pullup
• Pulldown
• Pullnone
• Pullup
• Pulldown
• Pullnone
• Pullup
• Pulldown
• Pullnone
• Pullup
• Pulldown
• Pullnone
• Pullup
• Pulldown
• Pullnone
• Pullup
• Pulldown
• Pullnone
Setting Bitstream Generator Options
Refer to the “BitGen” chapter in the Xilinx ISE^® software documentation.
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
126