XC3S5000-5FGG676C Datasheet, PDF (47/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Functional Description
The Standard Configuration Interface
Configuration signals belong to one of two different categories: Dedicated or Dual-Purpose. Which category determines
which of the FPGA’s power rails supplies the signal’s driver and, thus, helps describe the electrical characteristics at the pin.
The Dedicated configuration pins include PROG_B, HSWAP_EN, TDI, TMS, TCK, TDO, CCLK, DONE, and M0-M2. These
pins are powered by the V_CCAUX supply.
The Dual-Purpose configuration pins comprise INIT_B, DOUT, BUSY, RDWR_B, CS_B, and DIN/D0-D7. Each of these pins,
according to its bank placement, uses the V_CCO lines for either Bank 4 (VCCO_4 on most packages, VCCO_BOTTOM on
TQ144 and CP132 packages) or Bank 5 (VCCO_5). All the signals used in the serial configuration modes rely on VCCO_4
power. Signals used in the parallel configuration modes and Readback require from VCCO_5 as well as from VCCO_4.
Both the Dedicated signals described above and the Dual-Purpose signals constitute the configuration interface. The
Dedicated pins, powered by the 2.5V V_CCAUX supply, always use the LVCMOS25 I/O standard. The Dual-Purpose signals,
however, are powered by the VCCO_4 supply and also by the VCCO_5 supply in the Parallel configuration modes. The
simplest configuration interface uses 2.5V for VCCO_4 and VCCO_5, if required. However, VCCO_4 and, if needed,
VCCO_5 can be voltages other than 2.5V but then the configuration interface will have two voltage levels: 2.5V for V_CCAUX
and a separate V_CCO supply. The Dual-Purpose signals default to the LVCMOS input and output levels for the associated
V_CCO voltage supply.
3.3V-Tolerant Configuration Interface
A 3.3V-tolerant configuration interface simply requires adding a few external resistors as described in detail in XAPP453:
The 3.3V Configuration of Spartan-3 FPGAs.
The 3.3V-tolerance is implemented as follows (a similar approach can be used for other supply voltage levels):
Apply 3.3V to VCCO_4 and, in some configuration modes, to VCCO_5 to power the Dual-Purpose configuration pins. This
scales the output voltages and input thresholds associated with these pins so that they become 3.3V-compatible.
Apply 2.5V to V_CCAUX to power the Dedicated configuration pins. For 3.3V-tolerance, the Dedicated inputs require series
resistors to limit the incoming current to 10 mA or less. The Dedicated outputs have reduced noise margin when the FPGA
drives a High logic level into another device’s 3.3V receiver. Choose a power regulator or supply that can tolerate reverse
current on the V_CCAUX lines.
Configuration Modes
Spartan-3 FPGAs support the following five configuration modes:
• Slave Serial mode
• Master Serial mode
• Slave Parallel (SelectMAP) mode
• Master Parallel (SelectMAP) mode
• Boundary-Scan (JTAG) mode (IEEE 1532/IEEE 1149.1)
Slave Serial Mode
In Slave Serial mode, the FPGA receives configuration data in bit-serial form from a serial PROM or other serial source of
configuration data. The FPGA on the far right of Figure 26 is set for the Slave Serial mode. The CCLK pin on the FPGA is
an input in this mode. The serial bitstream must be set up at the DIN input pin a short time before each rising edge of the
externally generated CCLK.
Multiple FPGAs can be daisy-chained for configuration from a single source. After a particular FPGA has been configured,
the data for the next device is routed internally to the DOUT pin. The data on the DOUT pin changes on the falling edge of
CCLK.
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
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