XC3S5000-5FGG676C Datasheet, PDF(63/272 Page) Xilinx, Inc – Introduction and Ordering Information

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XC3S5000-5FGG676C Datasheet, PDF (63/272 Pages) Xilinx, Inc – Introduction and Ordering Information

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Spartan-3 FPGA Family: DC and Switching Characteristics

Table 35: Recommended Operating Conditions for User I/Os Using Single-Ended Standards

Signal Standard

(IOSTANDARD)

GTL(3)

GTL_DCI

GTLP(3)

GTLP_DCI

HSLVDCI_15

HSLVDCI_18

HSLVDCI_25

HSLVDCI_33

HSTL_I, HSTL_I_DCI

HSTL_III,

HSTL_III_DCI

HSTL_I_18,

HSTL_I_DCI_18

HSTL_II_18,

HSTL_II_DCI_18

HSTL_III_18,

HSTL_III_DCI_18

LVCMOS12

LVCMOS15,

LVDCI_15,

LVDCI_DV2_15

LVCMOS18,

LVDCI_18,

LVDCI_DV2_18

LVCMOS25(4,5),

LVDCI_25,

LVDCI_DV2_25(4)

LVCMOS33,

LVDCI_33,

LVDCI_DV2_33(4)

LVTTL

PCI33_3(7)

SSTL18_I,

SSTL18_I_DCI

SSTL18_II

SSTL2_I,

SSTL2_I_DCI

SSTL2_II,

SSTL2_II_DCI

Min (V)

â

â

â

â

1.4

1.7

2.3

3.0

1.4

1.4

1.7

1.7

1.7

1.14

1.4

1.7

2.3

3.0

3.0

3.0

1.7

1.7

2.3

2.3

VCCO

Nom (V)

â

1.2

â

1.5

1.5

1.8

2.5

3.3

1.5

1.5

1.8

1.8

1.8

1.2

1.5

1.8

2.5

3.3

3.3

3.3

1.8

1.8

2.5

2.5

Max (V)

â

â

â

â

1.6

1.9

2.7

3.465

1.6

1.6

1.9

1.9

1.9

1.3

1.6

1.9

2.7

3.465

3.465

3.465

1.9

1.9

2.7

2.7

Min (V)

0.74

0.74

0.88

0.88

â

â

â

â

0.68

â

0.8

â

â

â

â

â

â

â

â

â

0.833

0.833

1.15

1.15

VREF

Nom (V)

0.8

0.8

1

1

0.75

0.9

1.25

1.65

0.75

0.9

0.9

0.9

1.1

â

â

â

â

â

â

â

0.900

0.900

1.25

1.25

Max (V)

0.86

0.86

1.12

1.12

â

â

â

â

0.9

â

1.1

â

â

â

â

â

â

â

â

â

0.969

0.969

1.35

1.35

VIL

Max (V)

VREF â 0.05

VREF â 0.05

VREF â 0.1

VREF â 0.1

VREF â 0.1

VREF â 0.1

VREF â 0.1

VREF â 0.1

VREF â 0.1

VREF â 0.1

VREF â 0.1

VREF â 0.1

VREF â 0.1

0.37 VCCO

0.30 VCCO

0.30 VCCO

0.7

0.8

0.8

0.30 VCCO

VREF â 0.125

VREF â 0.125

VREF â 0.15

VREF â 0.15

VIH

Min (V)

VREF + 0.05

VREF + 0.05

VREF + 0.1

VREF + 0.1

VREF + 0.1

VREF + 0.1

VREF + 0.1

VREF + 0.1

VREF + 0.1

VREF + 0.1

VREF + 0.1

VREF + 0.1

VREF + 0.1

0.58 VCCO

0.70 VCCO

0.70 VCCO

1.7

2.0

2.0

0.50 VCCO

VREF + 0.125

VREF + 0.125

VREF + 0.15

VREF + 0.15

Notes:

1. Descriptions of the symbols used in this table are as follows:

VCCO â the supply voltage for output drivers as well as LVCMOS, LVTTL, and PCI inputs

VREF â the reference voltage for setting the input switching threshold

VIL â the input voltage that indicates a Low logic level

VIH â the input voltage that indicates a High logic level

2. For device operation, the maximum signal voltage (VIH max) may be as high as VIN max. See Table 28.

3. Because the GTL and GTLP standards employ open-drain output buffers, VCCO lines do not supply current to the I/O circuit, rather this current is

provided using an external pull-up resistor connected from the I/O pin to a termination voltage (VTT). Nevertheless, the voltage applied to the

associated VCCO lines must always be at or above VTT and I/O pad voltages.

4. There is approximately 100 mV of hysteresis on inputs using LVCMOS25 or LVCMOS33 standards.

5. All dedicated pins (M0-M2, CCLK, PROG_B, DONE, HSWAP_EN, TCK, TDI, TDO, and TMS) use the LVCMOS standard and draw power from the

VCCAUX rail (2.5V). The dual-purpose configuration pins (DIN/D0, D1-D7, CS_B, RDWR_B, BUSY/DOUT, and INIT_B) use the LVCMOS standard

before the user mode. For these pins, apply 2.5V to the VCCO Bank 4 and VCCO Bank 5 rails at power-on and throughout configuration. For information

concerning the use of 3.3V signals, see 3.3V-Tolerant Configuration Interface, page 47.

6. The Global Clock Inputs (GCLK0-GCLK7) are dual-purpose pins to which any signal standard can be assigned.

7. For more information, see XAPP457.

DS099 (v3.1) June 27, 2013

www.xilinx.com

Product Specification

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