XC3S5000-5FGG676C Datasheet, PDF (125/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Pinout Descriptions
Table 79: Pin Behavior After Power-Up, During Configuration (Cont’d)
Configuration Mode Settings <M2:M1:M0>
Pin Name
Serial Modes
SelectMap Parallel Modes
Master <0:0:0> Slave <1:1:1> Master <0:1:1> Slave <1:1:0>
VCCO: I/O bank output voltage supply pins
VCCO_4
Same voltage as Same voltage as Same voltage as Same voltage as
(for DUAL pins) external interface external interface external interface external interface
VCCO_5
(for DUAL pins)
VCCO_5
VCCO_5
Same voltage as Same voltage as
external interface external interface
VCCO_#
VCCO_#
VCCO_#
VCCO_#
VCCO_#
VCCAUX: Auxiliary voltage supply pins
VCCAUX
+2.5V
+2.5V
+2.5V
+2.5V
VCCINT: Internal core voltage supply pins
VCCINT
+1.2V
+1.2V
+1.2V
+1.2V
GND: Ground supply pins
GND
GND
GND
GND
GND
JTAG Mode
<1:0:1>
VCCO_4
VCCO_5
VCCO_#
+2.5V
+1.2V
GND
Bitstream
Configuration
Option
N/A
N/A
N/A
N/A
N/A
N/A
Notes:
1. #= I/O bank number, an integer from 0 to 7.
2. (I) = input, (O) = output, (OD) = open-drain output, (I/O) = bidirectional, (I/OD) = bidirectional with open-drain output. Open-drain output
requires pull-up to create logic High level.
3.
Shaded cell indicates that the pin is high-impedance during configuration. To enable a soft pull-up resistor during configuration, drive or
tie HSWAP_EN Low.
Bitstream Options
Table 80 lists the various bitstream options that affect pins on a Spartan-3 FPGA. The table shows the names of the affected
pins, describes the function of the bitstream option, the name of the bitstream generator option variable, and the legal values
for each variable. The default option setting for each variable is indicated with bold, underlined text.
Table 80: Bitstream Options Affecting Spartan-3 Device Pins
Affected Pin Name(s)
Bitstream Generation Function
All unused I/O pins of
type I/O, DUAL, GCLK,
DCI, VREF
IO_Lxxy_#/DIN,
IO_Lxxy_#/DOUT,
IO_Lxxy_#/INIT_B
IO_Lxxy_#/D0,
IO_Lxxy_#/D1,
IO_Lxxy_#/D2,
IO_Lxxy_#/D3,
IO_Lxxy_#/D4,
IO_Lxxy_#/D5,
IO_Lxxy_#/D6,
IO_Lxxy_#/D7,
IO_Lxxy_#/CS_B,
IO_Lxxy_#/RDWR_B,
IO_Lxxy_#/BUSY,
IO_Lxxy_#/INIT_B
For all I/O pins that are unused in the application after configuration, this
option defines whether the I/Os are individually tied to VCCO via a pull-up
resistor, tied ground via a pull-down resistor, or left floating. If left floating,
the unused pins should be connected to a defined logic level, either from
a source internal to the FPGA or external.
Serial configuration mode: If set to Yes, then these pins retain their
functionality after configuration completes, allowing for device
(re-)configuration. Readback is not supported in with serial mode.
Parallel configuration mode (also called SelectMAP): If set to Yes, then
these pins retain their SelectMAP functionality after configuration
completes, allowing for device readback and for partial or complete
(re-)configuration.
Option
Variable
Name
UnusedPin
Values
(Default)
• Pulldown
• Pullup
• Pullnone
Persist
Persist
• No
• Yes
• No
• Yes
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
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