XC3S5000-5FGG676C Datasheet, PDF (84/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: DC and Switching Characteristics
Simultaneously Switching Output Guidelines
This section provides guidelines for the maximum allowable number of Simultaneous Switching Outputs (SSOs). These
guidelines describe the maximum number of user I/O pins, of a given output signal standard, that should simultaneously
switch in the same direction, while maintaining a safe level of switching noise. Meeting these guidelines for the stated test
conditions ensures that the FPGA operates free from the adverse effects of ground and power bounce.
Ground or power bounce occurs when a large number of outputs simultaneously switch in the same direction. The output
drive transistors all conduct current to a common voltage rail. Low-to-High transitions conduct to the V_CCO rail; High-to-Low
transitions conduct to the GND rail. The resulting cumulative current transient induces a voltage difference across the
inductance that exists between the die pad and the power supply or ground return. The inductance is associated with
bonding wires, the package lead frame, and any other signal routing inside the package. Other variables contribute to SSO
noise levels, including stray inductance on the PCB as well as capacitive loading at receivers. Any SSO-induced voltage
consequently affects internal switching noise margins and ultimately signal quality.
Table 49 and Table 50 provide the essential SSO guidelines. For each device/package combination, Table 49 provides the
number of equivalent V_CCO/GND pairs. The equivalent number of pairs is based on characterization and will possibly not
match the physical number of pairs. For each output signal standard and drive strength, Table 50 recommends the maximum
number of SSOs, switching in the same direction, allowed per V_CCO/GND pair within an I/O bank. The Table 50 guidelines
are categorized by package style. Multiply the appropriate numbers from Table 49 and Table 50 to calculate the maximum
number of SSOs allowed within an I/O bank. Exceeding these SSO guidelines may result in increased power or ground
bounce, degraded signal integrity, or increased system jitter.
SSO_MAX/IO Bank = Table 49 x Table 50
The recommended maximum SSO values assume that the FPGA is soldered on the printed circuit board and that the board
uses sound design practices. The SSO values do not apply for FPGAs mounted in sockets, due to the lead inductance
introduced by the socket.
The number of SSOs allowed for quad-flat packages (VQ, TQ, PQ) is lower than for ball grid array packages (FG) due to the
larger lead inductance of the quad-flat packages. Ball grid array packages are recommended for applications with a large
number of simultaneously switching outputs.
Table 49: Equivalent V_CCO /GND Pairs per Bank
Device
VQ100 CP132 ⁽¹⁾⁽²⁾ TQ144⁽¹⁾ PQ208
XC3S50
1
1.5
1.5
2
XC3S200
1
–
1.5
2
XC3S400
–
–
1.5
2
XC3S1000
–
–
–
–
XC3S1500
–
–
–
–
XC3S2000
–
–
–
–
XC3S4000
–
–
–
–
XC3S5000
–
–
–
–
FT256
–
3
3
3
–
–
–
–
FG320
–
–
3
3
3
–
–
–
FG456
–
–
5
5
5
5
–
–
FG676
–
–
–
5
6
6
6
6
FG900
–
–
–
–
–
9
10
10
FG1156 ⁽²⁾
–
–
–
–
–
–
12
12
Notes:
1. The V_CCO lines for the pair of banks on each side of the CP132 and TQ144 packages are internally tied together. Each pair of interconnected
banks shares three V_CCO/GND pairs. Consequently, the per bank number is 1.5.
2. The CP132, CPG132, FG1156, and FGG1156 packages are discontinued. See
http://www.xilinx.com/support/documentation/spartan-3_customer_notices.htm.
3. The information in this table also applies to Pb-free packages.
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
84