XC3S5000-5FGG676C Datasheet, PDF (48/272 Pages) Xilinx, Inc – Introduction and Ordering Information

X-Ref Target - Figure 26
Spartan-3 FPGA Family: Functional Description
3.3V: XCF0xS
1.8V: XCFxxP
2.5V
2.5V
V_CCO
V_CCINT
V_CCJ
D0
Platform
Flash PROM
2.5V
XCF0xS
or
XCFxxP
CE
OE/RESET
CF
CLK
GND
All
4.7KΩ
V_CCO Bank 4
V_CCAUX V_CCINT
1.2V
DIN
DOUT
Spartan-3
FPGA
Master
M0
M1
M2
DONE
INIT_B
PROG_B
CCLK
GND
2.5V
V_CCO Bank 4
V_CCAUX V_CCINT
1.2V
DIN
Spartan-3
FPGA
2.5V
Slave
M0
M1
M2
DONE
INIT_B
PROG_B
CCLK
GND
Notes:
DS099_23_112905
1. There are two ways to use the DONE line. First, one may set the BitGen option DriveDone to "Yes" only for the last
FPGA to be configured in the chain shown above (or for the single FPGA as may be the case). This enables the DONE
pin to drive High; thus, no pull-up resistor is necessary. DriveDone is set to "No" for the remaining FPGAs in the chain.
Second, DriveDone can be set to "No" for all FPGAs. Then all DONE lines are open-drain and require the pull-up
resistor shown in grey. In most cases, a value between 3.3KΩ to 4.7KΩ is sufficient. However, when using DONE
synchronously with a long chain of FPGAs, cumulative capacitance may necessitate lower resistor values (e.g. down
to 330Ω) in order to ensure a rise time within one clock cycle.
2. For information on how to program the FPGA using 3.3V signals and power, see 3.3V-Tolerant Configuration Interface.
Figure 26: Connection Diagram for Master and Slave Serial Configuration
Slave Serial mode is selected by applying <111> to the mode pins (M0, M1, and M2). A pull-up on the mode pins makes
slave serial the default mode if the pins are left unconnected.
Master Serial Mode
In Master Serial mode, the FPGA drives CCLK pin, which behaves as a bidirectional I/O pin. The FPGA in the center of
Figure 26 is set for Master Serial mode and connects to the serial configuration PROM and to the CCLK inputs of any slave
FPGAs in a configuration daisy-chain. The master FPGA drives the configuration clock on the CCLK pin to the Xilinx Serial
PROM, which, in response, provides bit-serial data to the FPGA’s DIN input. The FPGA accepts this data on each rising
CCLK edge. After the master FPGA finishes configuring, it passes data on its DOUT pin to the next FPGA device in a
daisy-chain. The DOUT data appears after the falling CCLK clock edge.
The Master Serial mode interface is identical to Slave Serial except that an internal oscillator generates the configuration
clock (CCLK). A wide range of frequencies can be selected for CCLK, which always starts at a default frequency of 6 MHz.
Configuration bits then switch CCLK to a higher frequency for the remainder of the configuration.
Slave Parallel Mode (SelectMAP)
The Parallel or SelectMAP modes support the fastest configuration. Byte-wide data is written into the FPGA with a BUSY
flag controlling the flow of data. An external source provides 8-bit-wide data, CCLK, an active-Low Chip Select (CS_B) signal
and an active-Low Write signal (RDWR_B). If BUSY is asserted (High) by the FPGA, the data must be held until BUSY goes
Low. Data can also be read using the Slave Parallel mode. If RDWR_B is asserted, configuration data is read out of the
FPGA as part of a readback operation.
After configuration, it is possible to use any of the Multipurpose pins (DIN/D0-D7, DOUT/BUSY, INIT_B, CS_B, and
RDWR_B) as User I/Os. To do this, simply set the BitGen option Persist to No and assign the desired signals to multipurpose
configuration pins using the Xilinx development software. Alternatively, it is possible to continue using the configuration port
DS099 (v3.1) June 27, 2013
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Product Specification
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