XC3S5000-5FGG676C Datasheet, PDF (73/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: DC and Switching Characteristics
Table 43: Propagation Times for the IOB Input Path
Symbol
Description
Conditions
Propagation Times
T_IOPLI
The time it takes for data to travel
from the Input pin through the
IFF latch to the I output with no
input delay programmed
LVCMOS25⁽²⁾ ,
IOBDELAY = NONE
T_IOPLID
The time it takes for data to travel
from the Input pin through the
IFF latch to the I output with the
input delay programmed
LVCMOS25⁽²⁾ ,
IOBDELAY = IFD
Device
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
Speed Grade
-5
-4
Max
Max
Units
2.01
2.31
ns
1.50
1.72
ns
1.50
1.72
ns
2.01
2.31
ns
2.01
2.31
ns
2.01
2.31
ns
2.09
2.41
ns
2.18
2.51
ns
4.75
5.46
ns
4.89
5.62
ns
4.76
5.48
ns
5.38
6.18
ns
5.76
6.62
ns
7.04
8.09
ns
7.52
8.65
ns
7.69
8.84
ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 48 and are based on the operating conditions set forth in
Table 32 and Table 35.
2. This propagation time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. When this is
true, add the appropriate Input adjustment from Table 44.
Table 44: Input Timing Adjustments for IOB
Convert Input Time from LVCMOS25 to the
Following Signal Standard (IOSTANDARD)
Single-Ended Standards
GTL, GTL_DCI
GTLP, GTLP_DCI
HSLVDCI_15
HSLVDCI_18
HSLVDCI_25
HSLVDCI_33
HSTL_I, HSTL_I_DCI
HSTL_III, HSTL_III_DCI
HSTL_I_18, HSTL_I_DCI_18
HSTL_II_18, HSTL_II_DCI_18
HSTL_III_18, HSTL_III_DCI_18
LVCMOS12
Add the Adjustment Below
Speed Grade
-5
-4
0.44
0.50
0.36
0.42
0.51
0.59
0.29
0.33
0.51
0.59
0.51
0.59
0.51
0.59
0.37
0.42
0.36
0.41
0.39
0.45
0.45
0.52
0.63
0.72
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
73