XC3S5000-5FGG676C Datasheet, PDF (27/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Functional Description
X-Ref Target - Figure 14
WEA
ENA
SSRA
CLKA
ADDRA[r_A–1:0]
DIA[w_A–1:0]
DIPA[3:0]
RAMB16_Sw_A_Sw_B
DOPA[p_A–1:0]
DOA[w_A–1:0]
WEB
ENB
SSRB
CLKB
ADDRB[r_B–1:0]
DIB[w_B–1:0]
DIPB[3:0]
DOPB[p_B–1:0]
DOB[w_B–1:0]
WE
EN
SSR
CLK
ADDR[r–1:0]
DI[w–1:0]
DIP[p–1:0]
RAMB16_Sw
DOP[p–1:0]
DO[w–1:0]
(a) Dual-Port
(b) Single-Port
DS099-2_13_112905
Notes:
1. w_A and w_B are integers representing the total data path width (i.e., data bits plus parity bits) at ports A and B, respectively.
2. p_A and p_B are integers that indicate the number of data path lines serving as parity bits.
3. r_A and r_B are integers representing the address bus width at ports A and B, respectively.
4. The control signals CLK, WE, EN, and SSR on both ports have the option of inverted polarity.
Figure 14: Block RAM Primitives
Table 13: Block RAM Port Signals
Signal
Port A
Port B
Description Signal Name Signal Name
Address Bus
ADDRA
ADDRB
Data Input Bus
DIA
DIB
Parity Data
Input(s)
DIPA
DIPB
Direction
Input
Input
Input
Function
The Address Bus selects a memory location for read or write
operations. The width (w) of the port’s associated data path determines
the number of available address lines (r).
Whenever a port is enabled (ENA or ENB = High), address transitions
must meet the data sheet setup and hold times with respect to the port
clock (CLKA or CLKB). This requirement must be met, even if the RAM
read output is of no interest.
Data at the DI input bus is written to the addressed memory location
addressed on an enabled active CLK edge.
It is possible to configure a port’s total data path width (w) to be 1, 2, 4,
9, 18, or 36 bits. This selection applies to both the DI and DO paths of
a given port. Each port is independent. For a port assigned a width (w),
the number of addressable locations is 16,384/(w-p) where "p" is the
number of parity bits. Each memory location has a width of "w"
(including parity bits). See the DIP signal description for more
information of parity.
Parity inputs represent additional bits included in the data input path to
support error detection. The number of parity bits "p" included in the DI
(same as for the DO bus) depends on a port’s total data path width (w).
See Table 14.
DS099 (v3.1) June 27, 2013
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Product Specification
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