XC3S5000-5FGG676C Datasheet, PDF (33/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Functional Description
The DLL component has two clock inputs, CLKIN and CLKFB, as well as seven clock outputs, CLK0, CLK90, CLK180,
CLK270, CLK2X, CLK2X180, and CLKDV as described in Table 16. The clock outputs drive simultaneously; however, the
High Frequency mode only supports a subset of the outputs available in the Low Frequency mode. See DLL Frequency
Modes, page 35. Signals that initialize and report the state of the DLL are discussed in The Status Logic Component,
page 41.
Table 16: DLL Signals
Signal Direction
Description
Mode Support
Low
High
Frequency Frequency
CLKIN
Input Accepts original clock signal.
Yes
Yes
CLKFB
Input
Accepts either CLK0 or CLK2X as feed back signal. (Set CLK_FEEDBACK
attribute accordingly).
Yes
Yes
CLK0
Output Generates clock signal with same frequency and phase as CLKIN.
Yes
Yes
CLK90
Output Generates clock signal with same frequency as CLKIN, only phase-shifted 90°.
Yes
No
CLK180
Output Generates clock signal with same frequency as CLKIN, only phase-shifted 180°.
Yes
Yes
CLK270
Output Generates clock signal with same frequency as CLKIN, only phase-shifted 270°.
Yes
No
CLK2X
Output Generates clock signal with same phase as CLKIN, only twice the frequency.
Yes
No
CLK2X180
Output
Generates clock signal with twice the frequency of CLKIN, phase-shifted 180°
with respect to CLKIN.
Yes
No
CLKDV
Output
Divides the CLKIN frequency by CLKDV_DIVIDE value to generate lower
frequency clock signal that is phase-aligned to CLKIN.
Yes
Yes
The clock signal supplied to the CLKIN input serves as a reference waveform, with which the DLL seeks to align the
feedback signal at the CLKFB input. When eliminating clock skew, the common approach to using the DLL is as follows: The
CLK0 signal is passed through the clock distribution network to all the registers it synchronizes. These registers are either
internal or external to the FPGA. After passing through the clock distribution network, the clock signal returns to the DLL via
a feedback line called CLKFB. The control block inside the DLL measures the phase error between CLKFB and CLKIN. This
phase error is a measure of the clock skew that the clock distribution network introduces. The control block activates the
appropriate number of delay elements to cancel out the clock skew. Once the DLL has brought the CLK0 signal in phase with
the CLKIN signal, it asserts the LOCKED output, indicating a “lock” on to the CLKIN signal.
DLL Attributes and Related Functions
A number of different functional options can be set for the DLL component through the use of the attributes described in
Table 17. Each attribute is described in detail in the sections that follow:
Table 17: DLL Attributes
Attribute
CLK_FEEDBACK
DLL_FREQUENCY_MODE
CLKIN_DIVIDE_BY_2
CLKDV_DIVIDE
DUTY_CYCLE_CORRECTION
Description
Values
Chooses either the CLK0 or CLK2X output to drive the CLKFB input NONE, 1X, 2X
Chooses between High Frequency and Low Frequency modes
LOW, HIGH
Halves the frequency of the CLKIN signal just as it enters the DCM TRUE, FALSE
Selects constant used to divide the CLKIN input frequency to
generate the CLKDV output frequency
1.5, 2, 2.5, 3, 3.5, 4, 4.5,
5, 5.5, 6.0, 6.5, 7.0, 7.5,
8, 9, 10, 11, 12, 13, 14,
15, and 16.
Enables 50% duty cycle correction for the CLK0, CLK90, CLK180,
and CLK270 outputs
TRUE, FALSE
DS099 (v3.1) June 27, 2013
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Product Specification
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