XC3S5000-5FGG676C Datasheet, PDF (25/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Functional Description
Function Generator
Each of the two LUTs (F and G) in a slice have four logic inputs (A1-A4) and a single output (D). This permits any
four-variable Boolean logic operation to be programmed into them. Furthermore, wide function multiplexers can be used to
effectively combine LUTs within the same CLB or across different CLBs, making logic functions with still more input variables
possible.
The LUTs in both the right-hand and left-hand slice-pairs not only support the logic functions described above, but also can
function as ROM that is initialized with data at the time of configuration.
The LUTs in the left-hand slice-pair (even-numbered columns such as X0 in Figure 11) of each CLB support two additional
functions that the right-hand slice-pair (odd-numbered columns such as X1) do not.
First, it is possible to program the “left-hand LUTs” as distributed RAM. This type of memory affords moderate amounts of
data buffering anywhere along a data path. One left-hand LUT stores 16 bits. Multiple left-hand LUTs can be combined in
various ways to store larger amounts of data. A dual port option combines two LUTs so that memory access is possible from
two independent data lines. A Distributed ROM option permits pre-loading the memory with data during FPGA configuration.
Second, it is possible to program each left-hand LUT as a 16-bit shift register. Used in this way, each LUT can delay serial
data anywhere from one to 16 clock cycles. The four left-hand LUTs of a single CLB can be combined to produce delays up
to 64 clock cycles. The SHIFTIN and SHIFTOUT lines cascade LUTs to form larger shift registers. It is also possible to
combine shift registers across more than one CLB. The resulting programmable delays can be used to balance the timing
of data pipelines.
Block RAM Overview
All Spartan-3 devices support block RAM, which is organized as configurable, synchronous 18Kbit blocks. Block RAM stores
relatively large amounts of data more efficiently than the distributed RAM feature described earlier. (The latter is better
suited for buffering small amounts of data anywhere along signal paths.) This section describes basic Block RAM functions.
For more information, refer to the chapter entitled “Using Block RAM” in UG331.
The aspect ratio—i.e., width vs. depth—of each block RAM is configurable. Furthermore, multiple blocks can be cascaded
to create still wider and/or deeper memories.
A choice among primitives determines whether the block RAM functions as dual- or single-port memory. A name of the form
RAMB16_S[w_A]_S[w_B] calls out the dual-port primitive, where the integers w_A and w_B specify the total data path width at
ports w_A and w_B, respectively. Thus, a RAMB16_S9_S18 is a dual-port RAM with a 9-bit-wide Port A and an 18-bit-wide Port
B. A name of the form RAMB16_S[w] identifies the single-port primitive, where the integer w specifies the total data path
width of the lone port. A RAMB16_S18 is a single-port RAM with an 18-bit-wide port. Other memory functions—e.g., FIFOs,
data path width conversion, ROM, etc.—are readily available using the CORE Generator™ software, part of the Xilinx
development software.
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
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