XC3S5000-5FGG676C Datasheet, PDF (134/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Pinout Descriptions
Table 87: VQ100 Package Pinout (Cont’d)
Bank
XC3S50
XC3S200
Pin Name
VQ100
Pin
Number
VCCAUX TDO
P76
VCCAUX TMS
P78
Type
JTAG
JTAG
User I/Os by Bank
Table 88 indicates how the available user-I/O pins are distributed between the eight I/O banks on the VQ100 package.
Table 88: User I/Os Per Bank in VQ100 Package
Package Edge
Top
Right
Bottom
Left
I/O Bank Maximum I/O
I/O
0
6
1
1
7
2
2
8
5
3
8
5
4
10
0
5
8
0
6
8
4
7
8
5
All Possible I/O Pins by Type
DUAL
DCI
VREF
0
2
1
0
2
1
0
2
1
0
2
1
6
2
0
6
0
0
0
2
2
0
2
1
GCLK
2
2
0
0
2
2
0
0
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
134