XC3S5000-5FGG676C Datasheet, PDF (46/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Functional Description
Configuration
Spartan-3 devices are configured by loading application specific configuration data into the internal configuration memory.
Configuration is carried out using a subset of the device pins, some of which are "Dedicated" to one function only, while
others, indicated by the term "Dual-Purpose", can be re-used as general-purpose User I/Os once configuration is complete.
Depending on the system design, several configuration modes are supported, selectable via mode pins. The mode pins M0,
M1, and M2 are Dedicated pins. The mode pin settings are shown in Table 26.
Table 26: Spartan-3 FPGAs Configuration Mode Pin Settings
Configuration Mode⁽¹⁾
M0
M1
M2 Synchronizing Clock
Master Serial
0
0
0
CCLK Output
Slave Serial
1
1
1
CCLK Input
Master Parallel
1
1
0
CCLK Output
Slave Parallel
0
1
1
CCLK Input
JTAG
1
0
1
TCK Input
Data Width
1
1
8
8
1
Serial DOUT⁽²⁾
Yes
Yes
No
No
No
Notes:
1. The voltage levels on the M0, M1, and M2 pins select the configuration mode.
2. The daisy chain is possible only in the Serial modes when DOUT is used.
The HSWAP_EN input pin defines whether the I/O pins that are not actively used during configuration have pull-up resistors
during configuration. By default, HSWAP_EN is tied High (via an internal pull-up resistor if left floating) which shuts off the
pull-up resistors on the user I/O pins during configuration. When HSWAP_EN is tied Low, user I/Os have pull-ups during
configuration. The Dedicated configuration pins (CCLK, DONE, PROG_B, M2, M1, M0, HSWAP_EN) and the JTAG pins
(TDI, TMS, TCK, and TDO) always have a pull-up resistor to VCCAUX during configuration, regardless of the value on the
HSWAP_EN pin. Similarly, the dual-purpose INIT_B pin has an internal pull-up resistor to VCCO_4 or VCCO_BOTTOM,
depending on the package style.
Depending on the chosen configuration mode, the FPGA either generates a CCLK output, or CCLK is an input accepting an
externally generated clock.
A persist option is available which can be used to force the configuration pins to retain their configuration function even after
device configuration is complete. If the persist option is not selected then the configuration pins with the exception of CCLK,
PROG_B, and DONE can be used as user I/O in normal operation. The persist option does not apply to the boundary-scan
related pins. The persist feature is valuable in applications that readback configuration data after entering the User mode.
Table 27 lists the total number of bits required to configure each FPGA as well as the PROMs suitable for storing those bits.
See DS123: Platform Flash In-System Programmable Configuration PROMs data sheet for more information.
Table 27: Spartan-3 FPGA Configuration Data
Device
File Sizes
Xilinx Platform Flash PROM
Serial Configuration Parallel Configuration
XC3S50
439,264
XCF01S
XCF08P
XC3S200 1,047,616
XCF01S
XCF08P
XC3S400 1,699,136
XCF02S
XCF08P
XC3S1000 3,223,488
XCF04S
XCF08P
XC3S1500 5,214,784
XCF08P
XCF08P
XC3S2000 7,673,024
XCF08P
XCF08P
XC3S4000 11,316,864
XCF16P
XCF16P
XC3S5000 13,271,936
XCF16P
XCF16P
The maximum bitstream length that Spartan-3 FPGAs support in serial daisy-chains is 4,294,967,264 bits (4 Gbits), roughly
equivalent to a daisy-chain with 323 XC3S5000 FPGAs. This is a limit only for serial daisy-chains where configuration data
is passed via the FPGA’s DOUT pin. There is no such limit for JTAG chains.
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
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