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XC3S5000-5FGG676C Datasheet, PDF (188/272 Pages) Xilinx, Inc – Introduction and Ordering Information
Spartan-3 FPGA Family: Pinout Descriptions
FG456 Footprint
X-Ref Target - Figure 51
Left Half of FG456
Package (Top View)
XC3S400
(264 max. user I/O)
196
I/O: Unrestricted,
general-purpose user I/O
32
VREF: User I/O or input
voltage reference for bank
69
N.C.: Unconnected pins for
XC3S400 ()
XC3S1000, XC3S1500,
XC3S2000 (333 max user I/O)
261
I/O: Unrestricted,
general-purpose user I/O
36
VREF: User I/O or input
voltage reference for bank
0
N.C.: No unconnected pins
in this package
All devices
12
DUAL: Configuration pin,
then possible user I/O
8
GCLK: User I/O or global
clock buffer input
16
DCI: User I/O or reference
resistor input for bank
7
CONFIG: Dedicated
configuration pins
4
JTAG: Dedicated JTAG
port pins
12
VCCINT: Internal core
voltage supply (+1.2V)
40
VCCO: Output voltage
supply for bank
8
VCCAUX: Auxiliary voltage
supply (+2.5V)
52 GND: Ground
Bank 0
1
2
3
4
5
6
7
8
9
10 11
A
GND
PROG_B
IO
VREF_0
I/O
L01P_0
VRN_0
I/O
L09P_0
VCCAUX
I/O
L19P_0

I/O
L24P_0
I/O
L27P_0
I/O
I/O
L32P_0
GCLK6
B TDI
GND
HSWAP_
EN
I/O
L01N_0
VRP_0
I/O
L09N_0
I/O
L15P_0
I/O
L19N_0

I/O
L24N_0
I/O
L27N_0
I/O
L29P_0
I/O
L32N_0
GCLK7
I/O
C L16P_7
VREF_7
I/O
I/O
L01N_7
VRP_7
I/O
L01P_7
VRN_7
I/O
L06P_0
I/O
L15N_0
IO
VREF_0
VCCO_0
GND
I/O
L29N_0
I/O
L31P_0
VREF_0
D
I/O
L16N_7
I/O
L19P_7
I/O
L19N_7
VREF_7
I/O
L17P_7
I/O
I/O
L06N_0 L10P_0
I/O
L16P_0
I/O
L22P_0

I/O
I/O
I/O
L31N_0
IO
I/O
E
I/O
I/O
L21N_7 L21P_7
I/O
I/O VREF_0 I/O
I/O L22N_0 I/O
L20P_7 L17N_7  L10N_0 L16N_0  L25P_0
I/O
L28P_0
I/O
L30P_0
F
VCCAUX
I/O
L23N_7
I/O
L23P_7
I/O
L20N_7
I/O
L22P_7
I/O
IO
VREF_0
VCCO_0
I/O
L25N_0
I/O
L28N_0
I/O
L30N_0
G
I/O
L27N_7
I/O
L27P_7
VREF_7
I/O
I/O
L26N_7 L26P_7


I/O
L24P_7
I/O
L22N_7
VCCINT VCCINT
VCCO_0
VCCO_0
VCCO_0
I/O
I/O
I/O
H
L28N_7 L28P_7


VCCO_7
L29P_7

I/O
L24N_7
VCCO_7 VCCINT
I/O
I/O
I/O
I/O
I/O
J L32N_7 L32P_7 GND L29N_7 L31N_7 L31P_7 VCCO_7





GND GND GND
I/O
I/O
K
I/O
I/O
L35N_7 L35P_7
I/O
L34N_7
I/O L33N_7
L34P_7 
L33P_7 VCCO_7

GND GND GND
L
I/O
L40N_7
VREF_7
I/O
L40P_7
I/O
L39N_7
I/O
L39P_7
I/O
L38N_7
I/O
L38P_7
VCCO_7
GND GND GND
M
I/O
L40P_6
VREF_6
I/O
L40N_6
I/O
L39P_6
I/O
L39N_6
I/O
L38P_6
I/O
L38N_6
VCCO_6
GND GND GND
N
I/O
L35P_6
I/O
L35N_6
I/O
L34P_6
I/O
L34N_6
VREF_6
I/O
L33P_6

I/O
L33N_6 VCCO_6

GND GND GND
I/O
I/O
I/O
I/O
I/O
P L32P_6 L32N_6 GND L31P_6 L31N_6 L28P_6 VCCO_6





GND GND GND
I/O
I/O
I/O
I/O
R L29P_6 L29N_6 VCCO_6 L26P_6 L28N_6 VCCO_6 VCCINT




I/O
T
I/O
I/O L26N_6 I/O
L27P_6 L27N_6  L23P_6
I/O
L22P_6
I/O
L22N_6
VCCINT VCCINT VCCO_5
VCCO_5
VCCO_5
U
VCCAUX
I/O
L24P_6
I/O
L24N_6
VREF_6
I/O
L23N_6
I/O
IO
L19P_6 VREF_5
I/O
VCCO_5
I/O

I/O
I/O
V
I/O
L21P_6
I/O
I/O
I/O
I/O
L21N_6 L20P_6 L20N_6 L19N_6
I/O
L15P_5
I/O
I/O
I/O
L24P_5 L27P_5
I/O
I/O
L31P_5
D5
I/O
W L17P_6
VREF_6
I/O
L17N_6
I/O
I/O
L16P_6 L16N_6
I/O
L09P_5
I/O
L15N_5
I/O
L19P_5
VREF_5

I/O
L24N_5
I/O
I/O
L27N_5 L29P_5
VREF_5 VREF_5
I/O
L31N_5
D4
Y
I/O
I/O
L01P_6
VRN_6
I/O
L01N_6
VRP_6
I/O
L01N_5
RDWR_B
I/O
L09N_5
I/O
L16P_5
I/O
L19N_5

VCCO_5
GND
I/O
L29N_5
I/O
L32P_5
GCLK2
A
A
M1
GND
I/O
L01P_5
CS_B
I/O
L06P_5
I/O
L10P_5
VRN_5
I/O
L16N_5
I/O
L22P_5

I/O
L25P_5
I/O
L28P_5
D7
I/O
L30P_5
I/O
L32N_5
GCLK3
A
B
GND
M0
M2
I/O
L06N_5
I/O
L10N_5
VRP_5
I/O
VCCAUX L22N_5

I/O
L25N_5
I/O
L28N_5
D6
I/O
L30N_5
IO
VREF_5
Figure 51: FG456 Package Footprint (Top View)
Bank 5
DS099-4_11a_030203
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
188