XC3S5000-5FGG676C Datasheet, PDF (92/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: DC and Switching Characteristics
Table 56: Block RAM Timing
Symbol
Description
Clock-to-Output Times
T_BCKO
When reading from the Block RAM,
the time from the active transition at
the CLK input to data appearing at
the DOUT output
Setup Times
T_BDCK
Time from the setup of data at the
DIN inputs to the active transition at
the CLK input of the Block RAM
Hold Times
T_BCKD
Time from the active transition at the
Block RAM’s CLK input to the point
where data is last held at the DIN
inputs
Clock Timing
T_BPWH
Block RAM CLK signal High pulse
width
T_BPWL
Block RAM CLK signal Low pulse
width
Speed Grade
-5
-4
Min
Max
Min
Max
–
2.09
–
2.40
0.43
–
0.49
–
0
–
0
–
1.19
∞
1.37
∞
1.19
∞
1.37
∞
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 32.
2. For minimums, use the values reported by the Xilinx timing analyzer.
Units
ns
ns
ns
ns
ns
Clock Distribution Switching Characteristics
Table 57: Clock Distribution Switching Characteristics
Description
Symbol
Global clock buffer (BUFG, BUFGMUX, BUFGCE) I-input to O-output delay
Global clock multiplexer (BUFGMUX) select S-input setup to I0- and I1-inputs. Same
as BUFGCE enable CE-input
Notes:
1. For minimums, use the values reported by the Xilinx timing analyzer.
T_GIO
T_GSI
Maximum
Speed Grade
-5
-4
0.36
0.41
0.53
0.60
Units
ns
ns
DS099 (v3.1) June 27, 2013
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Product Specification
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