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| XC3S5000-5FGG676C Datasheet, PDF (18/272 Pages) Xilinx, Inc – Introduction and Ordering Information | |||
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Table 11: DCI Terminations
Termination
Controlled impedance output driver
Controlled output driver with half impedance
Spartan-3 FPGA Family: Functional Description
Schematic (1)
IOB
R
Z0
IOB
R/2
ds099_06a_070903
Z0
Signal Standards
(IOSTANDARD)
LVDCI_15
LVDCI_18
LVDCI_25
LVDCI_33
HSLVDCI_15
HSLVDCI_18
HSLVDCI_25
HSLVDCI_33
LVDCI_DV2_15
LVDCI_DV2_18
LVDCI_DV2_25
LVDCI_DV2_33
Single resistor
ds099_06b_070903
IOB
VCCO
GTL_DCI
GTLP_DCI
HSTL_III_DCI (2)
R
Z0
HSTL_III_DCI_18 (2)
Split resistors
IOB
ds099_06c_070903
VCCO
2R Z0
2R
Split resistors with output driver impedance fixed
to 25Ω
IOB
25Ω
ds099_06d_070903
VCCO
2R Z0
2R
HSTL_I_DCI (2)
HSTL_I_DCI_18 (2)
HSTL_II_DCI_18
DIFF_HSTL_II_18_DCI
DIFF_SSTL2_II_DCI
LVDS_25_DCI
LVDSEXT_25_DCI
SSTL18_I_DCI (3)
SSTL2_I_DCI (3)
SSTL2_II_DCI
ds099_06e_070903
Notes:
1. The value of R is equivalent to the characteristic impedance of the line connected to the I/O. It is also equal to half the value of RREF for the
DV2 standards and RREF for all other DCI standards.
2. For DCI using HSTL Classes I and III, terminations only go into effect at inputs (not at outputs).
3. For DCI using SSTL Class I, the split termination only goes into effect at inputs (not at outputs).
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
18
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