XC3S5000-5FGG676C Datasheet, PDF (69/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: DC and Switching Characteristics
I/O Timing
Table 40: Pin-to-Pin Clock-to-Output Times for the IOB Output Path
Symbol
Description
Conditions
Device
Clock-to-Output Times
T_ICKOFDCM
When reading from the Output
Flip-Flop (OFF), the time from the
active transition on the Global Clock pin
to data appearing at the Output pin.
The DCM is in use.
LVCMOS25⁽³⁾, 12 mA
output drive, Fast slew rate,
with DCM⁽⁴⁾
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
T_ICKOF
When reading from OFF, the time from
the active transition on the Global Clock
pin to data appearing at the Output pin.
The DCM is not in use.
LVCMOS25⁽³⁾, 12 mA
output drive, Fast slew rate,
without DCM
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
Speed Grade
-5
-4
Max⁽²⁾ Max⁽²⁾
Units
2.04
2.35
ns
1.45
1.75
ns
1.45
1.75
ns
2.07
2.39
ns
2.05
2.36
ns
2.03
2.34
ns
1.94
2.24
ns
2.00
2.30
ns
3.70
4.24
ns
3.89
4.46
ns
3.91
4.48
ns
4.00
4.59
ns
4.07
4.66
ns
4.19
4.80
ns
4.44
5.09
ns
4.38
5.02
ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 48 and are based on the operating conditions set forth in
Table 32 and Table 35.
2. For minimums, use the values reported by the Xilinx timing analyzer.
3. This clock-to-output time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or a
standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. If the former is true, add the appropriate
Input adjustment from Table 44. If the latter is true, add the appropriate Output adjustment from Table 47.
4. DCM output jitter is included in all measurements.
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
69