XC3S5000-5FGG676C Datasheet, PDF (187/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Pinout Descriptions
User I/Os by Bank
Table 101 indicates how the available user-I/O pins are distributed between the eight I/O banks for the XC3S400 in the
FG456 package. Similarly, Table 102 shows how the available user-I/O pins are distributed between the eight I/O banks for
the XC3S1000, XC3S1500, and XC3S2000 in the FG456 package.
Table 101: User I/Os Per Bank for XC3S400 in FG456 Package
Edge
I/O
Bank
Maximum I/O
I/O
All Possible I/O Pins by Type
DUAL
DCI
VREF
0
35
27
0
2
4
Top
1
35
27
0
2
4
2
31
25
0
2
4
Right
3
31
25
0
2
4
4
35
21
6
2
4
Bottom
5
35
21
6
2
4
6
31
25
0
2
4
Left
7
31
25
0
2
4
GCLK
2
2
0
0
2
2
0
0
Table 102: User I/Os Per Bank for XC3S1000, XC3S1500, and XC3S2000 in FG456 Package
Edge
I/O Bank Maximum I/O
I/O
All Possible I/O Pins by Type
DUAL
DCI
VREF
0
40
31
0
2
5
Top
1
40
31
0
2
5
2
43
37
0
2
4
Right
3
43
37
0
2
4
4
41
26
6
2
5
Bottom
5
40
25
6
2
5
6
43
37
0
2
4
Left
7
43
37
0
2
4
GCLK
2
2
0
0
2
2
0
0
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
187