XC3S5000-5FGG676C Datasheet, PDF (14/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Functional Description
ESD Protection
Clamp diodes protect all device pads against damage from Electro-Static Discharge (ESD) as well as excessive voltage
transients. Each I/O has two clamp diodes: One diode extends P-to-N from the pad to V_CCO and a second diode extends
N-to-P from the pad to GND. During operation, these diodes are normally biased in the off state. These clamp diodes are
always connected to the pad, regardless of the signal standard selected. The presence of diodes limits the ability of
Spartan-3 FPGA I/Os to tolerate high signal voltages. The V_IN absolute maximum rating in Table 28, page 58 specifies the
voltage range that I/Os can tolerate.
Slew Rate Control and Drive Strength
Two options, FAST and SLOW, control the output slew rate. The FAST option supports output switching at a high rate. The
SLOW option reduces bus transients. These options are only available when using one of the LVCMOS or LVTTL standards,
which also provide up to seven different levels of current drive strength: 2, 4, 6, 8, 12, 16, and 24 mA. Choosing the
appropriate drive strength level is yet another means to minimize bus transients.
Table 7 shows the drive strengths that the LVCMOS and LVTTL standards support.
Table 7: Programmable Output Drive Current
Signal Standard
(IOSTANDARD)
2
Current Drive (mA)
4 6 8 12 16 24
LVTTL
✓✓✓✓✓✓✓
LVCMOS33
✓✓✓✓✓✓✓
LVCMOS25
✓✓✓✓✓✓✓
LVCMOS18
✓✓✓✓✓✓ –
LVCMOS15
✓✓✓✓✓– –
LVCMOS12
✓✓✓– – – –
Boundary-Scan Capability
All Spartan-3 FPGA IOBs support boundary-scan testing compatible with IEEE 1149.1 standards. During boundary- scan
operations such as EXTEST and HIGHZ the I/O pull-down resistor is active. For more information, see Boundary-Scan
(JTAG) Mode, page 50, and refer to the “Using Boundary-Scan and BSDL Files” chapter in UG331.
SelectIO Interface Signal Standards
The IOBs support 18 different single-ended signal standards, as listed in Table 8. Furthermore, the majority of IOBs can be
used in specific pairs supporting any of eight differential signal standards, as shown in Table 9.
To define the SelectIO^™ interface signaling standard in a design, set the IOSTANDARD attribute to the appropriate setting.
Xilinx provides a variety of different methods for applying the IOSTANDARD for maximum flexibility. For a full description of
different methods of applying attributes to control IOSTANDARD, refer to the “Using I/O Resources” chapter in UG331.
Together with placing the appropriate I/O symbol, two externally applied voltage levels, V_CCO and V_REF, select the desired
signal standard. The V_CCO lines provide current to the output driver. The voltage on these lines determines the output
voltage swing for all standards except GTL and GTLP.
All single-ended standards except the LVCMOS, LVTTL, and PCI varieties require a Reference Voltage (V_REF) to bias the
input-switching threshold. Once a configuration data file is loaded into the FPGA that calls for the I/Os of a given bank to use
such a signal standard, a few specifically reserved I/O pins on the same bank automatically convert to V_REF inputs. When
using one of the LVCMOS standards, these pins remain I/Os because the V_CCO voltage biases the input-switching
threshold, so there is no need for V_REF. Select the V_CCO and V_REF levels to suit the desired single-ended standard according
to Table 8.
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
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