XC3S5000-5FGG676C Datasheet, PDF (35/272 Pages) Xilinx, Inc – Introduction and Ordering Information

X-Ref Target - Figure 21
BUFG
FPGA
CLK90
CLK180
CLKIN _CLK270
CLKDV
DCM _CLK2X
CLK2X180
CLKFB
CLK0
BUFGMUX
Clock
Net Delay
BUFGMUX
CLK0
(a) On-Chip with CLK0 Feedback
FPGA
IBUFG
IBUFG
CLK90
CLK180
CLKIN CLK270
CLKDV
DCM _CLK2X
CLK2X180
CLKFB
CLK0
OBUF
OBUF
Clock
Net Delay
Spartan-3 FPGA Family: Functional Description
BUFG
FPGA
CLK0
CLK90
CLKIN CLK180
CLK270
DCM CLKDV
CLK2X180
BUFGMUX
Clock
Net Delay
CLKFB
CLK2X
BUFGMUX
CLK2X
(b) On-Chip with CLK2X Feedback
FPGA
IBUFG
IBUFG
CLK0
CLK90
CLKIN CLK180
CLK270
DCM CLKDV
CLK2X180
CLKFB
CLK2X
OBUF
OBUF
Clock
Net Delay
CLK0
CLK2X
(c) Off-Chip with CLK0 Feedback
(d) Off-Chip with CLK2X Feedback
DS099-2_09_082104
Notes:
1. In the Low Frequency mode, all seven DLL outputs are available. In the High Frequency mode, only the CLK0, CLK180, and
CLKDV outputs are available.
Figure 21: Input Clock, Output Clock, and Feedback Connections for the DLL
In the on-chip synchronization case (the [a] and [b] sections of Figure 21), it is possible to connect any of the DLL’s seven
output clock signals through general routing resources to the FPGA’s internal registers. Either a Global Clock Buffer (BUFG)
or a BUFGMUX affords access to the global clock network. As shown in the [a] section of Figure 21, the feedback loop is
created by routing CLK0 (or CLK2X, in the [b] section) to a global clock net, which in turn drives the CLKFB input.
In the off-chip synchronization case (the [c] and [d] sections of Figure 21), CLK0 (or CLK2X) plus any of the DLL’s other
output clock signals exit the FPGA using output buffers (OBUF) to drive an external clock network plus registers on the
board. As shown in the [c] section of Figure 21, the feedback loop is formed by feeding CLK0 (or CLK2X, in the [d] section)
back into the FPGA using an IBUFG, which directly accesses the global clock network, or an IBUF. Then, the global clock net
is connected directly to the CLKFB input.
DLL Frequency Modes
The DLL supports two distinct operating modes, High Frequency and Low Frequency, with each specified over a different
clock frequency range. The DLL_FREQUENCY_MODE attribute chooses between the two modes. When the attribute is set
to LOW, the Low Frequency mode permits all seven DLL clock outputs to operate over a low-to-moderate frequency range.
When the attribute is set to HIGH, the High Frequency mode allows the CLK0, CLK180 and CLKDV outputs to operate at the
highest possible frequencies. The remaining DLL clock outputs are not available for use in High Frequency mode.
Accommodating High Input Frequencies
If the frequency of the CLKIN signal is high such that it exceeds the maximum permitted, divide it down to an acceptable
value using the CLKIN_DIVIDE_BY_2 attribute. When this attribute is set to TRUE, the CLKIN frequency is divided by a
factor of two just as it enters the DCM.
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
35