XC3S5000-5FGG676C Datasheet, PDF (156/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Pinout Descriptions
FT256: 256-lead Fine-pitch Thin Ball Grid Array
The 256-lead fine-pitch thin ball grid array package, FT256, supports three different Spartan-3 devices, including the
XC3S200, the XC3S400, and the XC3S1000. The footprints for all three devices are identical, as shown in Table 96 and
Figure 49.
All the package pins appear in Table 96 and are sorted by bank number, then by pin name. Pairs of pins that form a
differential I/O pair appear together in the table. The table also shows the pin number for each pin and the pin type, as
defined earlier.
An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at
http://www.xilinx.com/support/documentation/data_ sheets/s3_pin.zip.
Pinout Table
Table 96: FT256 Package Pinout
Bank
XC3S200, XC3S400, XC3S1000 FT256 Pin
Pin Name
Number
0
IO
A5
0
IO
A7
0
IO/VREF_0
A3
0
IO/VREF_0
D5
0
IO_L01N_0/VRP_0
B4
0
IO_L01P_0/VRN_0
A4
0
IO_L25N_0
C5
0
IO_L25P_0
B5
0
IO_L27N_0
E6
0
IO_L27P_0
D6
0
IO_L28N_0
C6
0
IO_L28P_0
B6
0
IO_L29N_0
E7
0
IO_L29P_0
D7
0
IO_L30N_0
C7
0
IO_L30P_0
B7
0
IO_L31N_0
D8
0
IO_L31P_0/VREF_0
C8
0
IO_L32N_0/GCLK7
B8
0
IO_L32P_0/GCLK6
A8
0
VCCO_0
E8
0
VCCO_0
F7
0
VCCO_0
F8
1
IO
A9
1
IO
A12
1
IO
C10
1
IO/VREF_1
D12
1
IO_L01N_1/VRP_1
A14
1
IO_L01P_1/VRN_1
B14
Type
I/O
I/O
VREF
VREF
DCI
DCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
GCLK
GCLK
VCCO
VCCO
VCCO
I/O
I/O
I/O
VREF
DCI
DCI
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
156