XC3S5000-5FGG676C Datasheet, PDF (74/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: DC and Switching Characteristics
Table 44: Input Timing Adjustments for IOB (Cont’d)
Convert Input Time from LVCMOS25 to the
Following Signal Standard (IOSTANDARD)
Add the Adjustment Below
Speed Grade
-5
-4
LVCMOS15
0.42
0.49
LVDCI_15
0.38
0.43
LVDCI_DV2_15
0.38
0.44
LVCMOS18
0.24
0.28
LVDCI_18
0.29
0.33
LVDCI_DV2_18
0.28
0.33
LVCMOS25
0
0
LVDCI_25
0.05
0.05
LVDCI_DV2_25
0.04
0.04
LVCMOS33, LVDCI_33, LVDCI_DV2_33
–0.05
–0.02
LVTTL
0.18
0.21
PCI33_3
0.20
0.22
SSTL18_I, SSTL18_I_DCI
0.39
0.45
SSTL18_II
0.39
0.45
SSTL2_I, SSTL2_I_DCI
0.40
0.46
SSTL2_II, SSTL2_II_DCI
0.36
0.41
Differential Standards
LDT_25 (ULVDS_25)
0.76
0.88
LVDS_25, LVDS_25_DCI
0.65
0.75
BLVDS_25
0.34
0.39
LVDSEXT_25, LVDSEXT_25_DCI
0.80
0.92
LVPECL_25
0.18
0.21
RSDS_25
0.43
0.50
DIFF_HSTL_II_18, DIFF_HSTL_II_18_DCI
0.34
0.39
DIFF_SSTL2_II, DIFF_SSTL2_II_DCI
0.65
0.75
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 48 and are based on
the operating conditions set forth in Table 32, Table 35, and Table 37.
2. These adjustments are used to convert input path times originally specified for the LVCMOS25
standard to times that correspond to other signal standards.
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
74