XC3S5000-5FGG676C Datasheet, PDF (110/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Pinout Descriptions
Table 70: Spartan-3 FPGA Pin Definitions (Cont’d)
Pin Name
Direction
Description
GCLK: Global clock buffer inputs
IO_Lxxy_#/GCLK0,
IO_Lxxy_#/GCLK1,
IO_Lxxy_#/GCLK2,
IO_Lxxy_#/GCLK3,
IO_Lxxy_#/GCLK4,
IO_Lxxy_#/GCLK5,
IO_Lxxy_#/GCLK6,
IO_Lxxy_#/GCLK7
Input if connected to global clock
buffers
Otherwise, same as I/O
Global Buffer Input:
Direct input to a low-skew global clock buffer. If not connected to a global
clock buffer, this pin is a user I/O.
VREF: I/O bank input reference voltage pins
IO_Lxxy_#/VREF_# or
IO/VREF_#
Voltage supply input when VREF
pins are used within a bank.
Otherwise, same as I/O
Input Buffer Reference Voltage for Special I/O Standards (per
bank):
If required to support special I/O standards, all the VREF pins within a bank
connect to a input threshold voltage source.
If not used as input reference voltage pins, these pins are available as
individual user-I/O pins.
CONFIG: Dedicated configuration pins (pull-up resistor to VCCAUX always active during configuration, regardless of
HSWAP_EN pin)
CCLK
Input in Slave configuration
modes
Output in Master configuration
modes
Configuration Clock:
The configuration clock signal synchronizes configuration data. This pin
has an internal pull-up resistor to VCCAUX during configuration.
PROG_B
Input
Program/Configure Device:
Active Low asynchronous reset to configuration logic. Asserting PROG_B
Low for an extended period delays the configuration process. This pin has
an internal pull-up resistor to VCCAUX during configuration.
DONE
Bidirectional with open-drain or
totem-pole Output
Configuration Done, Delay Start-up Sequence:
A Low-to-High output transition on this bidirectional pin signals the end of
the configuration process.
The FPGA produces a Low-to-High transition on this pin to indicate that the
configuration process is complete. The DriveDone bitstream generation
option defines whether this pin functions as a totem-pole output that
actively drives High or as an open-drain output. An open-drain output
requires a pull-up resistor to produce a High logic level. The open-drain
option permits the DONE lines of multiple FPGAs to be tied together, so
that the common node transitions High only after all of the FPGAs have
completed configuration. Externally holding the open-drain output Low
delays the start-up sequence, which marks the transition to user mode.
M0, M1, M2
Input
Configuration Mode Selection:
These inputs select the configuration mode. The logic levels applied to the
mode pins are sampled on the rising edge of INIT_B. See Table 75. These
pins have an internal pull-up resistor to VCCAUX during configuration,
making Slave Serial the default configuration mode.
HSWAP_EN
Input
Disable Pull-up Resistors During Configuration:
A Low on this pin enables pull-up resistors on all pins that are not actively
involved in the configuration process. A High value disables all pull-ups,
allowing the non-configuration pins to float.
JTAG: JTAG interface pins (pull-up resistor to VCCAUX always active during configuration, regardless of HSWAP_EN
pin)
TCK
Input
JTAG Test Clock:
The TCK clock signal synchronizes all JTAG port operations. This pin has
an internal pull-up resistor to VCCAUX during configuration.
DS099 (v3.1) June 27, 2013
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