XC3S5000-5FGG676C Datasheet, PDF (71/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: DC and Switching Characteristics
Table 41: System-Synchronous Pin-to-Pin Setup and Hold Times for the IOB Input Path (Cont’d)
Symbol
T_PHFD
Description
Conditions
When writing to IFF, the time from
the active transition at the Global
Clock pin to the point when data
must be held at the Input pin. The
DCM is not in use. The Input
Delay is programmed.
LVCMOS25⁽³⁾,
IOBDELAY = IFD,
without DCM
Device
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
Speed Grade
-5
-4
Min
Min
–0.98
–0.93
–0.40
–0.35
–0.27
–0.22
–1.19
–1.14
–1.43
–1.38
–2.33
–2.28
–2.47
–2.42
–2.66
–2.61
Units
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 48 and are based on the operating conditions set forth in
Table 32 and Table 35.
2. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, subtract the appropriate adjustment from Table 44. If this is true of the data Input, add the
appropriate Input adjustment from the same table.
3. This hold time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, add the appropriate Input adjustment from Table 44. If this is true of the data Input, subtract the
appropriate Input adjustment from the same table. When the hold time is negative, it is possible to change the data before the clock’s active
edge.
4. DCM output jitter is included in all measurements.
Table 42: Setup and Hold Times for the IOB Input Path
Symbol
Description
Conditions
Setup Times
T_IOPICK
Time from the setup of data at the Input pin
to the active transition at the ICLK input of
the Input Flip-Flop (IFF). No Input Delay is
programmed.
LVCMOS25⁽²⁾,
IOBDELAY = NONE
T_IOPICKD
Time from the setup of data at the Input pin LVCMOS25⁽²⁾,
to the active transition at the IFF’s ICLK IOBDELAY = IFD
input. The Input Delay is programmed.
Device
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
Speed Grade
-5
-4
Min
Min
Units
1.65
1.89
ns
1.37
1.57
ns
1.37
1.57
ns
1.65
1.89
ns
1.65
1.89
ns
1.65
1.89
ns
1.73
1.99
ns
1.82
2.09
ns
4.39
5.04
ns
4.76
5.47
ns
4.63
5.32
ns
5.02
5.76
ns
5.40
6.20
ns
6.68
7.68
ns
7.16
8.24
ns
7.33
8.42
ns
DS099 (v3.1) June 27, 2013
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Product Specification
71