XC3S5000-5FGG676C Datasheet, PDF (165/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Pinout Descriptions
FG320: 320-lead Fine-pitch Ball Grid Array
The 320-lead fine-pitch ball grid array package, FG320, supports three different Spartan-3 devices, including the XC3S400,
the XC3S1000, and the XC3S1500. The footprint for all three devices is identical, as shown in Table 98 and Figure 50.
The FG320 package is an 18 x 18 array of solder balls minus the four center balls.
All the package pins appear in Table 98 and are sorted by bank number, then by pin name. Pairs of pins that form a
differential I/O pair appear together in the table. The table also shows the pin number for each pin and the pin type, as
defined earlier.
An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at
http://www.xilinx.com/support/documentation/data_ sheets/s3_pin.zip.
Pinout Table
Table 98: FG320 Package Pinout
Bank
XC3S400, XC3S1000, XC3S1500
Pin Name
0
IO
0
IO
0
IO/VREF_0
0
IO/VREF_0
0
IO_L01N_0/VRP_0
0
IO_L01P_0/VRN_0
0
IO_L09N_0
0
IO_L09P_0
0
IO_L10N_0
0
IO_L10P_0
0
IO_L15N_0
0
IO_L15P_0
0
IO_L25N_0
0
IO_L25P_0
0
IO_L27N_0
0
IO_L27P_0
0
IO_L28N_0
0
IO_L28P_0
0
IO_L29N_0
0
IO_L29P_0
0
IO_L30N_0
0
IO_L30P_0
0
IO_L31N_0
0
IO_L31P_0/VREF_0
0
IO_L32N_0/GCLK7
0
IO_L32P_0/GCLK6
0
VCCO_0
0
VCCO_0
0
VCCO_0
FG320
Pin Number
D9
E7
B3
D6
A2
A3
B4
C4
C5
D5
A4
A5
B5
B6
C7
D7
C8
D8
E8
F8
A7
A8
B9
A9
E9
F9
B8
C6
G8
Type
I/O
I/O
VREF
VREF
DCI
DCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
GCLK
GCLK
VCCO
VCCO
VCCO
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
165