XC3S5000-5FGG676C Datasheet, PDF (93/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: DC and Switching Characteristics
Digital Clock Manager (DCM) Timing
For specification purposes, the DCM consists of three key components: the Delay-Locked Loop (DLL), the Digital Frequency
Synthesizer (DFS), and the Phase Shifter (PS).
Aspects of DLL operation play a role in all DCM applications. All such applications inevitably use the CLKIN and the CLKFB
inputs connected to either the CLK0 or the CLK2X feedback, respectively. Thus, specifications in the DLL tables (Table 58
and Table 59) apply to any application that only employs the DLL component. When the DFS and/or the PS components are
used together with the DLL, then the specifications listed in the DFS and PS tables (Table 60 through Table 63) supersede
any corresponding ones in the DLL tables. DLL specifications that do not change with the addition of DFS or PS functions
are presented in Table 58 and Table 59.
Period jitter and cycle-cycle jitter are two (of many) different ways of characterizing clock jitter. Both specifications describe
statistical variation from a mean value.
Period jitter is the worst-case deviation from the average clock period of all clock cycles in the collection of clock periods
sampled (usually from 100,000 to more than a million samples for specification purposes). In a histogram of period jitter, the
mean value is the clock period.
Cycle-cycle jitter is the worst-case difference in clock period between adjacent clock cycles in the collection of clock periods
sampled. In a histogram of cycle-cycle jitter, the mean value is zero.
Delay-Locked Loop (DLL)
Table 58: Recommended Operating Conditions for the DLL
Symbol
Description
Frequency Mode/
F_CLKIN Range
Input Frequency Ranges
F_CLKIN CLKIN_FREQ_DLL_LF Frequency for the CLKIN input
CLKIN_FREQ_DLL_HF
Input Pulse Requirements
CLKIN_PULSE
CLKIN pulse width as a
percentage of the CLKIN period
Input Clock Jitter Tolerance and Delay Path Variation⁽⁵⁾
CLKIN_CYC_JITT_DLL_LF
CLKIN_CYC_JITT_DLL_HF
Cycle-to-cycle jitter at the CLKIN
input
CLKIN_PER_JITT_DLL_LF
Period jitter at the CLKIN input
CLKIN_PER_JITT_DLL_HF
CLKFB_DELAY_VAR_EXT
Allowable variation of off-chip
feedback delay from the DCM
output to the CLKFB input
Low
High
F_CLKIN ≤ 100 MHz
F_CLKIN > 100 MHz
Low
High
All
All
Speed Grade
-5
-4
Min Max Min Max
Units
18⁽²⁾ 167⁽³⁾ 18⁽²⁾ 167⁽³⁾ MHz
48 280⁽³⁾ 48 280⁽³⁾⁽⁴⁾ MHz
40% 60% 40% 60%
-
45% 55% 45% 55%
-
– ±300 –
– ±150 –
–
±1
–
–
–
–
±1
–
±300 ps
±150 ps
±1
ns
±1
ns
Notes:
1. DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use.
2. The DFS, when operating independently of the DLL, supports lower F_CLKIN frequencies. See Table 60.
3. The CLKIN_DIVIDE_BY_2 attribute can be used to increase the effective input frequency range up to F_BUFG. When set to TRUE,
CLKIN_DIVIDE_BY_2 divides the incoming clock frequency by two as it enters the DCM.
4. Industrial temperature range devices have additional requirements for continuous clocking, as specified in Table 64.
5. CLKIN input jitter beyond these limits may cause the DCM to lose lock. See UG331 for more details.
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
93