XC3S5000-5FGG676C Datasheet, PDF (114/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Pinout Descriptions
Table 72: Dual-Purpose Configuration Pins for Parallel (SelectMAP) Configuration Modes
Pin Name Direction
Description
D0,
• Input during Configuration Data Port (high nibble):
D1,
configuration _{Collectively, the D0-D7 pins are the byte-wide configuration data port for the Parallel (SelectMAP)}
D2,
• Output during configuration modes. Configuration data is synchronized to the rising edge of CCLK clock signal.
D3
readback
The D0-D3 pins are the high nibble of the configuration data byte and located in Bank 4 and powered by
VCCO_4.
The BitGen option Persist permits this pin to retain its configuration function in the User mode.
D4,
• Input during Configuration Data Port (low nibble):
D5,
configuration _{The D4-D7 pins are the low nibble of the configuration data byte. However, these signals are located in}
D6,
• Output during Bank 5 and powered by VCCO_5.
D7
readback
The BitGen option Persist permits this pin to retain its configuration function in the User mode.
CS_B
Input
Chip Select for Parallel Mode Configuration:
Assert this pin Low, together with RDWR_B to write a configuration data byte from the D0-D7 bus to the
FPGA on a rising CCLK edge.
During Readback, assert this pin Low, along with RDWR_B High, to read a configuration data byte from
the FPGA to the D0-D7 bus on a rising CCLK edge.
This signal is located in Bank 5 and powered by VCCO_5.
The BitGen option Persist permits this pin to retain its configuration function in the User mode.
CS_B
0
1
Function
FPGA selected. SelectMAP inputs are valid on the next rising edge of CCLK.
FPGA deselected. All SelectMAP inputs are ignored.
RDWR_B
Input
Read/Write Control for Parallel Mode Configuration:
In Master and Slave Parallel modes, assert this pin Low together with CS_B to write a configuration data
byte from the D0-D7 bus to the FPGA on a rising CCLK edge. Once asserted during configuration,
RDWR_B must remain asserted until configuration is complete.
During Readback, assert this pin High with CS_B Low to read a configuration data byte from the FPGA
to the D0-D7 bus on a rising CCLK edge.
This signal is located in Bank 5 and powered by VCCO_5.
The BitGen option Persist permits this pin to retain its configuration function in the User mode.
RDWR_B
0
1
Function
If CS_B is Low, then load (write) configuration data to the FPGA.
This option is valid only if the Persist bitstream option is set to Yes. If CS_B is
Low, then read configuration data from the FPGA.
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
114