XC3S5000-5FGG676C Datasheet, PDF (103/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: DC and Switching Characteristics
X-Ref Target - Figure 39
TCK
(Input)
TMS
(Input)
TDI
(Input)
TDO
(Output)
T_TMSTCK
T_TDITCK
T_TCKTMS
T_TCKTDI
T_CCH
T_CCL
1/F_TCK
T_TCKTDO
Figure 39: JTAG Waveforms
DS099_06_102909
Table 68: Timing for the JTAG Test Access Port
Symbol
Description
Clock-to-Output Times
T_TCKTDO
The time from the falling transition on the TCK pin to data appearing at
the TDO pin
Setup Times
T_TDITCK
The time from the setup of data at the TDI pin to the rising transition at
the TCK pin
T_TMSTCK
The time from the setup of a logic level at the TMS pin to the rising
transition at the TCK pin
Hold Times
T_TCKTDI
The time from the rising transition at the TCK pin to the point when data
is last held at the TDI pin
T_TCKTMS
The time from the rising transition at the TCK pin to the point when a logic
level is last held at the TMS pin
Clock Timing
T_TCKH
T_TCKL
F_TCK
TCK pin High pulse width
TCK pin Low pulse width
Frequency of the TCK signal
JTAG Configuration
Boundary-Scan
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 32.
All Speed Grades
Min
Max
1.0
11.0
7.0
–
7.0
–
0
–
0
–
5
∞
5
∞
0
33
0
25
Units
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
103