XC3S5000-5FGG676C Datasheet, PDF (89/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: DC and Switching Characteristics
Internal Logic Timing
Table 51: CLB Timing
Symbol
Description
Clock-to-Output Times
T_CKO
When reading from the FFX (FFY) Flip-Flop, the time
from the active transition at the CLK input to data
appearing at the XQ (YQ) output
Setup Times
T_AS
Time from the setup of data at the F or G input to the
active transition at the CLK input of the CLB
T_DICK
Time from the setup of data at the BX or BY input to
the active transition at the CLK input of the CLB
Hold Times
T_AH
Time from the active transition at the CLK input to
the point where data is last held at the F or G input
T_CKDI
Time from the active transition at the CLK input to
the point where data is last held at the BX or BY input
Clock Timing
T_CH
CLB CLK signal High pulse width
T_CL
CLB CLK signal Low pulse width
F_TOG
Maximum toggle frequency (for export control)
Propagation Times
T_ILO
The time it takes for data to travel from the CLB’s
F (G) input to the X (Y) output
Set/Reset Pulse Width
T_{RPW_CLB}
The minimum allowable pulse width, High or Low, to
the CLB’s SR input
Speed Grade
-5
-4
Min
Max
Min
Max
–
0.63
–
0.72
0.46
–
0.53
–
1.27
–
1.57
–
0
–
0
–
0.25
–
0.29
–
0.69
∞
0.79
∞
0.69
∞
0.79
∞
–
725
–
630
–
0.53
–
0.61
0.76
–
0.87
–
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 32.
2. The timing shown is for SLICEM.
3. For minimums, use the values reported by the Xilinx timing analyzer.
Units
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
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