XC3S5000-5FGG676C Datasheet, PDF (28/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Functional Description
Table 13: Block RAM Port Signals (Cont’d)
Signal
Description
Port A
Port B
Signal Name Signal Name
Direction
Function
Data Output Bus
DOA
DOB
Output
Basic data access occurs whenever WE is inactive. The DO outputs
mirror the data stored in the addressed memory location.
Data access with WE asserted is also possible if one of the following two
attributes is chosen: WRITE_FIRST and READ_FIRST. WRITE_FIRST
simultaneously presents the new input data on the DO output port and
writes the data to the address RAM location. READ_FIRST presents the
previously stored RAM data on the DO output port while writing new
data to RAM.
A third attribute, NO_CHANGE, latches the DO outputs upon the
assertion of WE.
It is possible to configure a port’s total data path width (w) to be 1, 2, 4,
9, 18, or 36 bits. This selection applies to both the DI and DO paths. See
the DI signal description.
Parity Data
Output(s)
DOPA
DOPB
Output
Parity inputs represent additional bits included in the data input path to
support error detection. The number of parity bits "p" included in the DI
(same as for the DO bus) depends on a port’s total data path width (w).
See Table 14.
Write Enable
WEA
WEB
Input
When asserted together with EN, this input enables the writing of data
to the RAM. In this case, the data access attributes WRITE_FIRST,
READ_FIRST or NO_CHANGE determines if and how data is updated
on the DO outputs. See the DO signal description.
When WE is inactive with EN asserted, read operations are still
possible. In this case, a transparent latch passes data from the
addressed memory location to the DO outputs.
Clock Enable
ENA
ENB
Input
When asserted, this input enables the CLK signal to synchronize Block
RAM functions as follows: the writing of data to the DI inputs (when WE
is also asserted), the updating of data at the DO outputs as well as the
setting/resetting of the DO output latches.
When de-asserted, the above functions are disabled.
Set/Reset
SSRA
SSRB
Input
When asserted, this pin forces the DO output latch to the value that the
SRVAL attribute is set to. A Set/Reset operation on one port has no
effect on the other ports functioning, nor does it disturb the memory’s
data contents. It is synchronized to the CLK signal.
Clock
CLKA
CLKB
Input
This input accepts the clock signal to which read and write operations
are synchronized. All associated port inputs are required to meet setup
times with respect to the clock signal’s active edge. The data output bus
responds after a clock-to-out delay referenced to the clock signal’s
active edge.
Port Aspect Ratios
On a given port, it is possible to select a number of different possible widths (w – p) for the DI/DO buses as shown in
Table 14. These two buses always have the same width. This data bus width selection is independent for each port. If the
data bus width of Port A differs from that of Port B, the Block RAM automatically performs a bus-matching function. When
data are written to a port with a narrow bus, then read from a port with a wide bus, the latter port will effectively combine
“narrow” words to form “wide” words. Similarly, when data are written into a port with a wide bus, then read from a port with
a narrow bus, the latter port will divide “wide” words to form “narrow” words. When the data bus width is eight bits or greater,
extra parity bits become available. The width of the total data path (w) is the sum of the DI/DO bus width and any parity bits
(p ).
The width selection made for the DI/DO bus determines the number of address lines according to the relationship expressed
below:
r = 14 – [log(w–p)/log(2)]
Equation 1
In turn, the number of address lines delimits the total number (n) of addressable locations or depth according to the following
equation:
n = 2^r
Equation 2
DS099 (v3.1) June 27, 2013
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