HD6417034 Datasheet, PDF (97/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

4.5 Instruction Exceptions
4.5.1 Types of Instruction Exceptions
Table 4.8 shows the three types of instruction that start exception handling (trap instructions,
illegal slot instructions, and general illegal instructions).
Table 4.8 Types of Instruction Exceptions
Type
Source Instruction
Trap instruction TRAPA
Illegal slot
instruction
Undefined code or instruction
that rewrites the PC located
immediately after a delayed
branch instruction (delay slot)
General illegal Undefined code in other than
instructions
delay slot
Comments
—
Delayed branch instructions are: JMP, JSR,
BRA, BSR, RTS, RTE. Instructions that
rewrite the PC are: JMP, JSR, BRA, BSR,
RTS, RTE, BT, BF, and TRAPA
—
4.5.2 Trap Instruction
Trap instruction exception handling is carried out when a trap instruction (TRAPA) is executed.
The CPU then:
1. Saves the status register by pushing register contents onto the stack.
2. Pushes the program counter value onto the stack. The PC value saved is the start address of the
next instruction after the TRAPA instruction.
3. Reads the exception handling routine start address from the vector table corresponding to the
vector number specified in the TRAPA instruction, branches to that address, and starts
program execution. The branch is not a delayed branch.
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