HD6417034 Datasheet, PDF (146/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

Table 8.4 summarizes read cycle state information.
Table 8.4 Read Cycle States
Read Cycle States
External Memory Space
Internal Space
WAIT Pin
Bits 15–8: Input
External Memory
RW7–RW0 Signal Space
Multi- On-Chip On-Chip
plexed Supporting ROM and
DRAM Space I/O
Modules RAM
0
Not
Areas 1, 3–5,7: 1 Column add- 4 states 3 states, 1 state,
sampled state, fixed
ress cycle: 1 + wait fixed
fixed
during
read
cycle*¹
Areas 0, 2, 6: 1 state ^{state, fixed}
+ long wait state
(short pitch)
states
from
WAIT
1
Sampled Areas 1, 3–5, 7: 2 Column address
during states + wait states cycle: 2 states +
read cycle from WAIT
wait state from
(Initial
value)
Areas 0, 2, 6: 1 state ^{WAIT (long}
+ long wait state + ^pitch)*2
wait state from WAIT
Notes: *1 Sampled in the address/data multiplexed I/O space
*2 During a CBR refresh, the WAIT signal is ignored and the wait state from the RLW1 and
RLW0 bits in RCR is inserted.
• Bits 7–2 (Reserved): These bits are always read as 1. The write value should always be 1.
• Bit 1 (Wait State Control During Write (WW1)): WW1 determines the number of states in
write cycles for the DRAM space (area 1) and whether or not to sample the WAIT signal.
When the DRAM enable bit (DRAME) in BCR is set to 1 and area 1 is being used as DRAM
space, clearing WW1 to 0 makes the column address output cycle finish in 1 state (short pitch).
When WW1 is set to 1, it finishes in 2 states plus the wait states from the WAIT signal (long
pitch).
Note: Write 0 to WW1 only when area 1 is used as DRAM space (DRAME bit in BCR is 1).
Never write 0 to WW1 when area 1 is used as external memory space (DRAME is 0).
Bit 1: WW1
0
1
DRAM Space (DRAME = 1)
Column address cycle: 1 state (short pitch)
Column address cycle: 2 states + wait state
from WAIT (long pitch)
(Initial value)
Area 1 External Memory Space
(DRAME = 0)
Setting inhibited
2 states + wait state from WAIT
• Bit 0 (Reserved): This bit is always read as 1. The write value should always be 1.
110