HD6417034 Datasheet, PDF (82/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

From any state when
RES = 0 and NMI = 1
From any state when
RES = 0 and NMI = 0
Power-on reset state
RES = 0, NMI = 0
RES = 0, NMI = 1
Manual reset state
When an interrupt source
or DMA address error occurs
RES = 1,
NMI = 1
RES = 1,
NMI = 0
Exception handling state
Reset states
Bus request
cleared
Bus request
generated
Bus-release-state
Exception
handling
source occurs
NMI interrupt
source occurs
Exception
handling
ends
Bus request
generated
Bus request
cleared
Bus request
generated
Bus request
cleared
Program execution state
SLEEP instruction
with SBY bit cleared
SLEEP
instruction with
SBY bit set
Sleep mode
Standby mode
Power-down state
Figure 2.6 Transitions Between Processing States
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