HD6417034 Datasheet, PDF (153/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

8.2.6 Refresh Control Register (RCR)
The refresh control register (RCR) is a 16-bit read/write register that controls the start of refresh-
ing and selects the refresh mode and the number of wait states during refreshing. It is initialized to
H'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode.
To prevent RCR from being written incorrectly, it must be written by a different method from
most other registers. A word transfer operation is used, H'5A is written in the upper byte, and the
actual data is written in the lower byte. For details, see section 8.2.11, Notes on Register Access.
Bit: 15
14
13
12
11
10
9
8
Bit name: —
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: —
—
—
—
—
—
—
—
Bit: 7
6
5
4
3
2
1
0
Bit name: RFSHE RMODE RLW1 RLW0 —
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W
—
—
—
—
• Bit 15–8 (Reserved): These bits are always read as 0.
• Bit 7 (Refresh Control (RFSHE)): RFSHE determines whether or not to perform DRAM
refresh operations. When this bit is cleared to 0, no DRAM refresh control is performed and
the refresh timer counter (RTCNT) can be used as an 8-bit interval timer. When set to 1,
DRAM refresh control is performed.
Bit 7: RFSHE
0
1
Description
Refresh control disabled. RTCNT can be used as an 8-bit interval
timer
(Initial value)
Refresh control enabled
• Bit 6 (Refresh Mode (RMODE)): When DRAM refresh control is selected (RFSHE = 1),
RMODE selects whether to perform CAS-before-RAS (CBR) refresh or self-refresh. When
this bit is cleared to 0, a CBR refresh is performed at the cycle set in the refresh timer
control/status register (RTCSR) and refresh time constant register (RTCOR). When set to 1,
the DRAM performs a self-refresh. When refresh control is not selected (RFSHE = 0), the
RMODE bit setting is not valid. When canceling self-refresh, set RMODE to 0 with RFSHE
set to 1.
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