HD6417034 Datasheet, PDF (220/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

• Bit 7 (Acknowledge Mode Bit (AM)): In dual address mode, AM selects whether the DACK
signal is output during the data read cycle or write cycle. This bit is valid only in channels 0
and 1. The AM bit is initialized to 0 by a reset and in standby mode. The AM bit is not valid in
single address mode.
Bit 7: AM
0
1
Description
DACK is output in read cycle
DACK is output in write cycle
(Initial value)
• Bit 6 (Acknowledge Level Bit (AL)): AL selects active-high or active-low for the DACK
signal. This bit is valid only in channels 0 and 1. The AL bit is initialized to 0 by a reset and in
standby mode.
Bit 6: AL
0
1
Description
DACK is active-high
DACK is active-low
(Initial value)
• Bit 5 (DREQ Select Bit (DS)): DS selects the DREQ input detection method used. This bit is
valid only in channels 0 and 1. The DS bit is initialized to 0 by a reset and in standby mode.
Bit 5: DS
0
1
Description
DREQ detected by low level
DREQ detected by falling edge
(Initial value)
• Bit 4 (Transfer Bus Mode Bit (TM)): TM selects the bus mode for DMA transfers. The TM bit
is initialized to 0 by a reset and in standby mode. When the source of the transfer request is an
on-chip supporting module, see table 9.4, Selecting On-Chip Peripheral Module Request
Modes with the RS Bits.
Bit 4: TM
0
1
Description
Cycle-steal mode
Burst mode
(Initial value)
• Bit 3 (Transfer Size Bit (TS)): TS selects the transfer unit size. If the on-chip supporting
module that is the source or destination of the transfer can only be accessed in bytes, byte must
be selected with this bit. The TS bit is initialized to 0 by a resets and in standby mode.
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