HD6417034 Datasheet, PDF (95/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

4.4 Interrupts
4.4.1 Interrupt Sources
Table 4.6 lists the types of interrupt exception handling sources (NMI, user break, IRQ, on-chip
supporting module).
Table 4.6 Interrupt Sources
Interrupt
NMI
User break
IRQ
On-chip supporting
module
Requesting Pin or Module
NMI pin (external input)
User break controller
IRQ0–IRQ7 pin (external input)
Direct Memory Access Controller
16-bit integrated timer pulse unit
Serial communication interface
A/D converter
Watchdog timer
Bus state controller
Number of Sources
1
1
8
4
15
8
1
1
2
Each interrupt source has a different vector number and vector address offset value. See table 5.3,
Interrupt Exception Vectors and Rankings, in section 5, Interrupt Controller (INTC), for details on
vector numbers and vector table address offsets.
4.4.2 Interrupt Priority Rankings
Interrupt sources are assigned priorities. When multiple interrupts occur at the same time, the
interrupt controller (INTC) ascertains their priorities and starts exception handling based on its
findings. Priorities from 16–0 can be assigned, with 0 the lowest level and 16 the highest. NMI has
priority level 16 and cannot be masked. NMI is always accepted. The user break priority level is
15. The IRQ and on-chip supporting module interrupt priority levels can be set in interrupt priority
level registers A–E (IPRA–IPRE) as shown in table 4.7. Priority levels 0–15 can be set. See
section 5.3.1, Interrupt Priority Registers A-E (IPRA–IPRE), for details.
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