HD6417034 Datasheet, PDF (645/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

Table A.43 WCR2 Bit Functions
Bit Bit Name
15–8 Single mode
DMA memory
read wait state
control (DRW7–
DRW0)
7–0 Single mode
DMA memory
write wait state
control (DWW7–
DWW0)
Description
Number of Single Mode DMA
External Space Cycle States
WAIT Pin External
DRAM
Value Signal Input Memory Space Space
Multiplex
I/O
0
Not sampled ^{• Areas 1, 3–5, 7:} Column
Wait state is 4
during single ^{fixed at 1 cycle} address cycle: cycles plus
mode DMA • Areas 0, 2, 6: Fixed at 1 WAIT
memory read 1 cycle + long cycle (short-
cycle
wait state
pitch)
1
Sampled
• Areas 1, 3–5, 7: Column
during single ^{wait state is 2} address cycle:
mode DMA ^{cycles plus}
memory read ^WAIT
Wait state is 2
cycles plus
cycle
• Areas 0, 2, 6: ^{WAIT (long-}
(Initial value) ^{1 cycle + long pitch)}
wait state, or
wait state from
WAIT
0
Not sampled ^{• Areas 1, 3–5, 7:} Column
Wait state is 4
during single ^{fixed at 1 cycle} address cycle: cycles plus
mode DMA • Areas 0, 2, 6: Fixed at 1 WAIT
memory write 1 cycle + long cycle (short-
cycle
wait state
pitch)
1
Sampled
• Areas 1, 3–5, 7: Column
during single ^{wait state is 2} address cycle:
mode DMA ^{cycles plus}
memory write ^WAIT
Wait state is 2
cycles plus
cycle
• Areas 0, 2, 6: ^{WAIT (long-}
(Initial value) ^{1 cycle + long pitch)}
wait state, or
wait state from
WAIT
609