HD6417034 Datasheet, PDF (30/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

12.4.5 Internal Reset With Watchdog Timer .................................................................. 347
Section 13 Serial Communication Interface (SCI) .................................................... 349
13.1 Overview............................................................................................................................ 349
13.1.1 Features ................................................................................................................ 349
13.1.2 Block Diagram...................................................................................................... 350
13.1.3 Input/Output Pins.................................................................................................. 351
13.1.4 Register Configuration ......................................................................................... 351
13.2 Register Descriptions......................................................................................................... 352
13.2.1 Receive Shift Register .......................................................................................... 352
13.2.2 Receive Data Register .......................................................................................... 352
13.2.3 Transmit Shift Register ........................................................................................ 353
13.2.4 Transmit Data Register......................................................................................... 353
13.2.5 Serial Mode Register ............................................................................................ 354
13.2.6 Serial Control Register ......................................................................................... 356
13.2.7 Serial Status Register............................................................................................ 359
13.2.8 Bit Rate Register (BRR)....................................................................................... 363
13.3 Operation ........................................................................................................................... 372
13.3.1 Overview .............................................................................................................. 372
13.3.2 Operation in Asynchronous Mode........................................................................ 374
13.3.3 Multiprocessor Communication ........................................................................... 385
13.3.4 Synchronous Operation ........................................................................................ 393
13.4 SCI Interrupt Sources and the DMAC............................................................................... 403
13.5 Usage Notes ....................................................................................................................... 403
Section 14 A/D Converter ................................................................................................. 407
14.1 Overview............................................................................................................................ 407
14.1.1 Features ................................................................................................................ 407
14.1.2 Block Diagram...................................................................................................... 408
14.1.3 Configuration of Input Pins.................................................................................. 409
14.1.4 Configuration of A/D Registers............................................................................ 410
14.2 Register Descriptions......................................................................................................... 410
14.2.1 A/D Data Registers A–D (ADDRA–ADDRD).................................................... 410
14.2.2 A/D Control/Status Register (ADCSR)................................................................ 411
14.2.3 A/D Control Register (ADCR)............................................................................. 413
14.3 CPU Interface .................................................................................................................... 414
14.4 Operation ........................................................................................................................... 416
14.4.1 Single Mode (SCAN = 0) ..................................................................................... 416
14.4.2 Scan Mode (SCAN = 1) ....................................................................................... 418
14.4.3 Input Sampling Time and A/D Conversion Time ................................................ 420
14.4.4 A/D Conversion Start by External Trigger Input ................................................. 421
14.5 Interrupts and DMA Transfer Requests ............................................................................ 421
14.6 Definitions of A/D Conversion Accuracy ......................................................................... 422
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