HD6417034 Datasheet, PDF (324/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

CK
TCNT
Overflow
signal
OVF
H' FFFF
H' 0000
OVI
Figure 10.56 Timing of Setting OVF
10.5.2 Status Flag Clear Timing
The status flags are cleared by being read by the CPU when set to 1, then being written with 0.
This timing is shown in figure 10.57.
TSR write cycle
T1
T2
T3
CK
Address
IMF, OVF
TSR address
Figure 10.57 Timing of Status Flag Clearing
288