HD6417034 Datasheet, PDF (386/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

• Four types of interrupts: Transmit-data-empty, transmit-end, receive-data-full, and receive-
error interrupts are requested independently. The transmit-data-empty and receive-data-full
interrupts can start the direct memory access controller (DMAC) to transfer data.
13.1.2 Block Diagram
Figure 13.1 shows a block diagram of the SCI.
Module data bus
RxD
TxD
SCK
RDR
RSR
TDR
SSR
BRR
SCR
TSR
SMR
Transmit/
receive control
Baud rate
generator
Parity
generation
Clock
Parity check
External clock
SCI
RSR: Receive shift register
RDR: Receive data register
TSR: Transmit shift register
TDR: Transmit data register
SMR: Serial mode register
SCR: Serial control register
SSR: Serial status register
BRR: Bit rate register
Figure 13.1 Block Diagram of SCI
Internal
data bus
φ
φ/4
φ/16
φ/64
TEI
TXI
RXI
ERI
350