HD6417034 Datasheet, PDF (233/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

9.3.4 DMA Transfer Types
The DMAC supports the transfers shown in table 9.5. It can operate in single address mode or dual
address mode, which are defined by how many bus cycles the DMAC takes to access the transfer
source and transfer destination. The actual transfer operation timing varies with the bus mode. The
DMAC has two bus modes: cycle-steal mode and burst mode.
Table 9.5 Supported DMA Transfers
Source
External
Device with
DACK
External device with
DACK
Not available
External memory
Single
Memory-mapped external Single
device
On-chip memory
Not available
On-chip supporting
module
Not available
Single: Single address mode
Dual: Dual address mode
Destination
External
Memory
Memory-
Mapped
External
Device
On-Chip
Memory
Single Single
Not available
On-Chip
Supporting
Module
Not available
Dual
Dual
Dual
Dual
Dual
Dual
Dual
Dual
Dual
Dual
Dual
Dual
Dual
Dual
Dual
Dual
Address Modes:
• Single Address Mode
In single address mode, both the transfer source and destination are external; one (selectable) is
accessed by a DACK signal while the other is accessed by an address. In this mode, the
DMAC performs the DMA transfer in 1 bus cycle by simultaneously outputting a transfer
request acknowledge DACK signal to one external device to access it while outputting an
address to the other end of the transfer. Figure 9.6 shows an example of a transfer between an
external memory and an external device with DACK in which the external device outputs data
to the data bus while that data is written in external memory in the same bus cycle.
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