HD6417034 Datasheet, PDF (178/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

8.5 DRAM Interface Operation
When the DRAM enable bit (DRAME) in BCR is set to 1, area 1 becomes DRAM space and the
DRAM interface function is available, which permits direct connection of this chip to DRAMs.
8.5.1 DRAM Address Multiplexing
When the multiplex enable bit (MXE) in the DRAM area control register (DCR) is set to 1, row
addresses and column addresses are multiplexed. This allows DRAMs that require multiplexing of
row and column addresses to be connected directly to an SH microprocessor without additional
multiplexing circuits. When addresses are multiplexed (MXE = 1), setting of the DCR’s multiplex
shift bits (MXC1, MXC0) allows selection of eight, nine and ten-bit row address shifting. Table
8.10 illustrates the relationship between the MXC1/MXC0 bits and address multiplexing.
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