HD6417034 Datasheet, PDF (393/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

• Bit 6 (Receive Interrupt Enable (RIE)): RIE enables or disables the receive-data-full interrupt
(RXI) requested when the receive data register full bit (RDRF) in the serial status register
(SSR) is set to 1 due to transfer of serial receive data from RSR to RDR. Also enables or
disables receive-error interrupt (ERI) requests.
Bit 6: RIE
0
1
Description
Receive-data-full interrupt (RXI) and receive-error interrupt (ERI)
requests are disabled
(Initial value)
RXI and ERI interrupt requests can be cleared by reading the RDRF
flag or error flag (FER, PER, or ORER) after it has been set to 1, then
clearing the flag to 0, or by clearing RIE to 0.
Receive-data-full interrupt (RXI) and receive-error interrupt (ERI)
requests are enabled
Bit 5 (Transmit Enable (TE)): TE enables or disables the SCI transmitter.
Bit 5: TE
0
1
Description
Transmitter disabled
(Initial value)
The transmit data register empty bit (TDRE) in the serial status register
(SSR) is fixed at 1.
Transmitter enabled. Serial transmission starts when the transmit data
register empty (TDRE) bit in the serial status register (SSR) is cleared
to 0 after writing transmit data into TDR. Select the transmit format in
SMR before setting TE to 1.
• Bit 4 (Receive Enable (RE)): RE enables or disables the SCI receiver.
Bit 4: RE
0
1
Description
Receiver disabled
(Initial value)
Clearing RE to 0 does not affect the receive flags (RDRF, FER, PER,
ORER). These flags retain their previous values.
Receiver enabled. Serial reception starts when a start bit is detected in
asynchronous mode, or serial clock input is detected in synchronous
mode. Select the receive format in SMR before setting RE to 1.
• Bit 3 (Multiprocessor Interrupt Enable (MPIE)): MPIE enables or disables multiprocessor
interrupts. The MPIE setting is used only in asynchronous mode, and only if the
multiprocessor mode bit (MP) in the serial mode register (SMR) is set to 1 during reception.
The MPIE setting is ignored in synchronous mode or when the MP bit is cleared to 0.
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