HD6417034 Datasheet, PDF (13/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

Section
10.4.6
Complementary
PWM Mode
Procedure for
Selecting
Complementary
PWM Mode (Figure
10.33):
10.6.15 ITU
Operating Modes
Table 10.18 ITU
Operating Modes
(Channel 0)
Table 10.19 ITU
Operating Modes
(Channel 1)
Table 10.20 ITU
Operating Modes
(Channel 2)
12.1.4 Register
Configuration
Table 12.2 WDT
Registers
Page
271
301
302
303
337
Description
Edition
Description amended
6
3. Set bits CMD1 and CMD0 in TMDB to select complementary PWM
mode. TIOCA3, TIOCB3, TIOCA4, TIOCB4, TOCXA4, and
TOCXB4 become PWM pins.
Table amended
Register Setting
TSNC
TMDR
TFCR
TOCR
TIOR0
Reset
Output
Operating
Comp Sync
Level
Mode
Sync MDF FDIR PWM PWM PWM Buffer Select IOA
IOB
Synch- SYNC0 — — √
———
—
√
√
ronized = 1
preset
PWM
√
— — PWM0 — — —
—
—
√*
=1
Output √
compare A
function
— — PWM0 — — —
—
IOA2 = 0, √
=0
others:
don’t care
6
TCR0
Clear Clock
Select Select
√
√
√
√
√
√
Table amended
Register Setting
TSNC
TMDR
TFCR
TOCR
TIOR1
Reset
Output
Operating
Comp Sync
Level
Mode
Sync MDF FDIR PWM PWM PWM Buffer Select IOA
IOB
Synch- SYNC1 — — √
———
—
√
√
ronized = 1
preset
PWM
√
— — PWM1 — — —
—
—
√*
=1
Output √
compare A
function
— — PWM1 — — —
—
IOA2 = 0, √
=0
others:
don’t care
6
TCR1
Clear Clock
Select Select
√
√
√
√
√
√
Table amended
Register Setting
TSNC
TMDR
TFCR
TOCR
TIOR2
Reset
Output
Operating
Comp Sync
Level
Mode
Sync MDF FDIR PWM PWM PWM Buffer Select IOA
IOB
Synch-
ronized
preset
SYNC2 — — √
=1
———
PWM
√
— — PWM2 — — —
=1
Output √
compare A
function
— — PWM2 — — —
=0
—
√
√
—
—
√*
—
IOA2 = 0, √
others:
don’t care
6
TCR2
Clear Clock
Select Select
√
√
√
√
√
√
*4 added
6
Name
Abbreviation R/W
Initial
Value
Address*⁴
Write*¹
Read*²
Timer control/status register TCSR
R/(W)*³ H'18
H'5FFFFB8 H'5FFFFB8
Timer counter
TCNT
R/W H'00
H'5FFFFB9
Reset control/status register RSTCSR
R/(W)*³ H'1F
H'5FFFFBA H'5FFFFBB
Notes: *1 Write by word transfer. A byte or longword write cannot be used.
*2 Read by byte transfer. The correct value cannot be obtained by a word or longword
read.
*3 Only 0 can be written in bit 7, to clear the flag.
*4 Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For
details on the register addresses, see section 8.3.5, Area Descriptions