HD6417034 Datasheet, PDF (446/691 Pages) Renesas Technology Corp – SuperH RISC ENGINE SH7032 AND SH7034

14.1.4 Configuration of A/D Registers
The A/D converter includes the registers listed in table 14.2.
Table 14.2 A/D Registers
Register Name
Abbreviation R/W
Initial Value Address*¹ Access Size
A/D data register A (high) ADDRAH
R
H'00
H'05FFFEE0 8, 16
A/D data register A (low) ADDRAL
R
H'00
H'05FFFEE1 16
A/D data register B (high) ADDRBH
R
H'00
H'05FFFEE2 8, 16
A/D data register B (low) ADDRBL
R
H'00
H'05FFFEE3 16
A/D data register C (high) ADDRCH
R
H'00
H'05FFFEE4 8, 16
A/D data register C (low) ADDRCL
R
H'00
H'05FFFEE5 16
A/D data register D (high) ADDRDH
R
H'00
H'05FFFEE6 8, 16
A/D data register D (low) ADDRDL
R
H'00
H'05FFFEE7 16
A/D control/status
register
ADCSR
R/(W)*² H'00
H'05FFFEE8 8, 16
A/D control register
ADCR
R/W H'7F
H'05FFFEE9 8, 16
Notes: *1 Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For
details on the register addresses, see section 8.3.5, Area Descriptions.
*2 Only 0 can be written in bit 7, to clear the flag.
14.2 Register Descriptions
14.2.1 A/D Data Registers A–D (ADDRA–ADDRD)
The four A/D data registers (ADDRA–ADDRD) are 16-bit read-only registers that store the
results of the A/D conversion. Each result consists of 10 bits. The first 8 bits are stored in the
upper byte of the data register corresponding to the selected channel. The last two bits are stored in
the lower byte of the data register. Bits 5–0 of the lower byte are reserved and are always read as
0. Each data register is assigned to two analog input channels (table 14.3).
The A/D data registers are always readable by the CPU. The upper byte can be read directly and
the lower byte is read via a temporary register (TEMP). See section 14.3, CPU Interface, for
details. The A/D data registers are initialized to H'0000 by a reset and in standby mode.
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